Abstract: A dynamic random access memory device includes a substrate having an active area, a stacked structure and a capacitor contact structure. The stacked structure is formed over the substrate and includes a bit line structure, a mask structure and a spacer structure. The bit line structure on the substrate is electrically connected to the active area. The mask structure is formed on the bit line structure and includes the first, second and third dielectric layers that are sequentially formed on the bit line structure. The dielectric constant of the second dielectric layer is less than the dielectric constant of each of the second and third dielectric layers. The spacer structure is formed on sidewalls of the bit line structure and the mask structure. The capacitor contact structure formed on the substrate is laterally separated from the stacked structure. The capacitor contact structure is electrically connected to the active area.

Abstract: A heat flow control method, for a data center cooling system, includes determining a plurality of features corresponding to a current scene of the data center cooling system at a first time point; and determining a plurality of cooling parameters at a second time point according to the plurality of features; wherein the data center cooling system utilizes the plurality of cooling parameters to control heat flow at the second time point; wherein the second time point lags the first time point.

Abstract: A computer-implemented method for artificial intelligence (AI) based risk/value assessment of a geographic area includes performing feature engineering to contextually enrich collected data. Three datasets are generated from the contextually enriched data, where a first dataset is generated by combining positive samples of the contextually enriched collected data with hard negative samples of the contextually enriched data, a second dataset is generated by combining the positive samples with soft negative samples of the contextually enriched data, and a third dataset is generated by combining the positive samples, hard negative samples, and soft negative samples. A machine learning model is trained to generate three different types of predictions for the risk/value assessment of the geographic area based on the three generated datasets.

Abstract: A semiconductor device includes a first well region laterally separated from a second well region in a substrate, a shallow trench isolation (STI) structure laterally between the first well region and the second well region in the substrate, a first implant region of a dopant type opposite to a dopant type of the first well region in the substrate, disposed vertically lower than the STI structure and laterally between the first well region and a lateral center of the STI structure, and a second implant region of a dopant type opposite to a dopant type of the second well region in the substrate, disposed vertically lower than the STI structure and laterally between the second well region and the lateral center of the STI structure.

Abstract: A modifiable hydrogel material has main chain polymers which are modified with anchor modules in the form of predetermined functionalized single strands of DNA. The main chain polymers can be crosslinked with one another by intermolecular DNA double strand formation. A DNA sequence of the anchor modules has a predetermined number of specific sequence positions N with different base combinations and/or is blocked by a temperature-dependent DNA blocking strand. In a method for producing a hydrogel with the modifiable hydrogel material, DNA modules in the form of free DNA single strands or DNA modules in the form of predetermined DNA single strand pairs which bind to anchor modules in a complementary manner are employed for crosslinking the main chain polymers, which form an intermolecular DNA double strand at a common binding domain.

Abstract: A semiconductor package including at least one functional die; at least one dummy die free of active circuit, wherein the dummy die comprises at least one metal-insulator-metal (MIM) capacitor; and a redistribution layer (RDL) structure interconnecting the MIM capacitor to the at least one functional die.

Abstract: A semiconductor package structure includes a substrate having a substrate having a first surface and second surface opposite thereto, wherein the substrate comprises a wiring structure. The structure also has a first semiconductor die disposed on the first surface of the substrate and electrically coupled to the wiring structure, and a second semiconductor die disposed on the first surface and electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged in a side-by-side manner. A molding material surrounds the first semiconductor die and the second semiconductor die, wherein the first semiconductor die is separated from the second semiconductor die by the molding material. Finally, an annular frame mounted on the first surface of the substrate, wherein the annular frame surrounds the first semiconductor die and the second semiconductor die.

Abstract: Provided are a dynamic random access memory and a method for manufacturing the same. The DRAM includes: a plurality of word line structures, located in a substrate; a plurality of bit line structures, located above the substrate, crossing over the plurality of word line structures; a plurality of node contacts, each of which being located between adjacent two of the word line structures and adjacent two of the bit line structures; and a plurality of first spacers, separating the plurality of node contacts. Each of the plurality of first spacers further comprises: spacer material, filled in a gap between the node contacts that are adjacent; and a first cap layer, embedded in the spacer material.

Abstract: A method for forming semiconductor structures is provided. The method includes forming a first patterning photoresist layer having a first opening on a first patterning layer, trimming the first patterning photoresist layer, transferring the first pattern of the trimmed first patterning photoresist layer to the first patterning layer, performing a first pattern reversal process to reverse the first pattern of the first patterning layer into the second opening, forming a second patterning layer in and on the second opening, forming a second patterning photoresist layer having a third opening on the second patterning layer, transferring the second pattern of the second patterning photoresist layer to a first stacking layer, performing a second pattern reversal process to reverse a third pattern between the second opening and the third opening into a fourth opening, and extending the fourth opening to the substrate.

Abstract: The present invention provides a motorcycle floor mat including a base and a telescopic bracket. The base is adapted to be placed on a foot pedal and has a receiving groove. The telescopic bracket is arranged in the receiving groove and adapted to extend from the receiving groove, and a storage space is formed between the telescopic bracket and the base. The present invention further provides a motorcycle including the above telescopic bracket.

Abstract: The present invention provides a motorcycle floor mat including a base and a folding bracket. The base is adapted to be placed on a foot pedal and has a receiving groove. The folding bracket is pivotally connected to the receiving groove and adapted to be raised from the receiving groove. The present invention further provides a motorcycle including the above folding bracket.

Abstract: A semiconductor device including a substrate, a capacitor, a stop layer, a first contact, and a second contact is provided. The substrate includes a memory array region and a peripheral circuit region. The capacitor is located in the memory array region. The capacitor includes a first electrode, a second electrode, and an insulating layer. The second electrode is located on the first electrode. The insulating layer is located between the first electrode and the second electrode. The stop layer is located on the second electrode in the memory array region and extends into the peripheral circuit region. A material of the stop layer is not a conductive material. The first contact is located in the memory array region, passes through the stop layer, and is electrically connected to the second electrode. The second contact is located in the peripheral circuit region and passes through the stop layer.

Abstract: A semiconductor package structure includes a substrate, a bridge structure, a redistribution layer, a first semiconductor component, and a second semiconductor component. The substrate has a wiring structure. The bridge structure is over the substrate. The redistribution layer is over the bridge structure. The first semiconductor component and the second semiconductor component are over the redistribution layer, wherein the first semiconductor component is electrically coupled to the second semiconductor component through the redistribution layer and the bridge structure.

Abstract: A semiconductor device including a substrate, a capacitor, a stop layer, a first contact, and a second contact is provided. The substrate includes a memory array region and a peripheral circuit region. The capacitor is located in the memory array region. The capacitor includes a first electrode, a second electrode, and an insulating layer. The second electrode is located on the first electrode. The insulating layer is located between the first electrode and the second electrode. The stop layer is located on the second electrode in the memory array region and extends into the peripheral circuit region. A material of the stop layer is not a conductive material. The first contact is located in the memory array region, passes through the stop layer, and is electrically connected to the second electrode. The second contact is located in the peripheral circuit region and passes through the stop layer.

Abstract: A semiconductor package structure includes a base having a first surface and a second surface opposite thereto, wherein the base comprises a wiring structure, a first electronic component disposed over the first surface of the base and electrically coupled to the wiring structure, a second electronic component disposed over the first surface of the base and electrically coupled to the wiring structure, wherein the first electronic component and the second electronic component are separated by a molding material, a first hole and a second hole formed on the second surface of the base, and a frame disposed over the first surface of the base, wherein the frame surrounds the first electronic component and the second electronic component.

Abstract: A semiconductor package structure includes a substrate having a wiring structure. A first semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure. A second semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged side-by-side. Holes are formed on a surface of the substrate, wherein the holes are located within a projection of the first semiconductor die or the second semiconductor die on the substrate. Further, a molding material surrounds the first semiconductor die and the second semiconductor die, and surfaces of the first semiconductor die and the second semiconductor die facing away from the substrate are exposed by the molding material.

Abstract: A semiconductor structure includes a substrate and a buried gate structure in the substrate. The buried gate structure includes a gate dielectric layer formed on the sidewall and the bottom surface of a trench in the substrate, a barrier layer formed in the trench and on the sidewall and the bottom surface of the gate dielectric layer, a first work function layer formed in the trench and including a main portion and a protruding portion, a second work function layer formed at opposite sides of the protruding portion, and an insulating layer formed in the trench and on the protruding portion of the first work function layer and the second work function layer. The barrier layer surrounds the main portion of the first work function layer. The area of the top surface of the protruding portion is less than the area of the bottom surface of the protruding portion.

Abstract: A virtual metrology method using a convolutional neural network (CNN) is provided. In this method, a dynamic time warping (DTW) algorithm is used to delete unsimilar sets of process data, and adjust the sets of process data to be of the same length, thereby enabling the CNN to be used for virtual metrology. A virtual metrology model of the embodiments of the present invention includes several CNN models and a conjecture model, in which plural inputs of the CNN model are sets of time sequence data of respective parameters, and plural outputs of the CNN models are inputs to the conjecture model.

Abstract: An electronic package includes a base of a rectangular shape, and a chip package including a first interface circuit die and a second interface circuit die. The first interface circuit die and second interface circuit die are mounted on a redistribution layer structure and encapsulated within a molding compound. The chip package is mounted on a top surface of the base and rotated relative to the base above a vertical axis that is orthogonal to the top surface through a rotation offset angle. A metal ring is mounted on the top surface of the base.

Abstract: A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor component, a conductive pillar, and a second semiconductor component. The redistribution layer is over the substrate. The first semiconductor component is over the redistribution layer. The conductive pillar is adjacent to the first semiconductor component, wherein the first semiconductor component and the conductive pillar are surrounded by a molding material. The second semiconductor component is over the molding material, wherein the second semiconductor component is electrically coupled to the redistribution layer through the conductive pillar.