Patents by Inventor Hsuan Peng

Hsuan Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11469152
    Abstract: A semiconductor chip package includes a substrate having a top surface and a bottom surface, and a semiconductor device mounted on the top surface of the substrate. A gap is provided between the semiconductor device and the top surface of the substrate. A pre-cut laminate epoxy sheet is disposed on the top surface of the substrate and around a perimeter of the semiconductor device.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: October 11, 2022
    Assignee: MEDIATEK INC.
    Inventors: Yi-Lin Tsai, Yi-Jou Lin, I-Hsuan Peng, Wen-Sung Hsu
  • Publication number: 20220262691
    Abstract: A semiconductor package includes a package substrate having a top surface and a bottom surface, and a stiffener ring mounted on the top surface of the package substrate. The stiffener ring includes a reinforcement rib that is coplanar with the stiffener ring on the top surface of the package substrate. At least two compartments are defined by the stiffener ring and the reinforcement rib. At least two individual chip packages are mounted on chip mounting regions within the at least two compartments, respectively, thereby constituting a package array on the package substrate.
    Type: Application
    Filed: March 2, 2022
    Publication date: August 18, 2022
    Applicant: Media Tek Inc.
    Inventors: Chi-Wen Pan, I-Hsuan Peng, Sheng-Liang Kuo, Yi-Jou Lin, Tai-Yu Chen
  • Patent number: 11410936
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate having a first surface and a second surface opposite thereto, wherein the substrate includes a wiring structure, and a first semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure. The package further includes a second semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are separated by a molding material. A first hole and a second hole are formed on the second surface of the substrate. Finally, a frame is disposed over the first surface of the substrate, wherein the frame surrounds the first semiconductor die and the second semiconductor die.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: August 9, 2022
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Chia-Cheng Chang, I-Hsuan Peng, Nai-Wei Liu
  • Publication number: 20220139848
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a semiconductor die disposed over the substrate, and a frame disposed over the substrate. The frame is adjacent to the semiconductor die, and an upper surface of the frame is lower than the upper surface of the semiconductor die. IN addition, a passive component is disposed on the substrate and located between the frame and the semiconductor die.
    Type: Application
    Filed: January 14, 2022
    Publication date: May 5, 2022
    Inventors: Chia-Cheng CHANG, Tzu-Hung LIN, I-Hsuan PENG, Yi-Jou LIN
  • Patent number: 11302592
    Abstract: A semiconductor package includes a package substrate having a top surface and a bottom surface, and a stiffener ring mounted on the top surface of the package substrate. The stiffener ring includes a reinforcement rib that is coplanar with the stiffener ring on the top surface of the package substrate. At least two compartments are defined by the stiffener ring and the reinforcement rib. At least two individual chip packages are mounted on chip mounting regions within the at least two compartments, respectively, thereby constituting a package array on the package substrate.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: April 12, 2022
    Assignee: MediaTek Inc.
    Inventors: Chi-Wen Pan, I-Hsuan Peng, Sheng-Liang Kuo, Yi-Jou Lin, Tai-Yu Chen
  • Publication number: 20220108954
    Abstract: An electronic package includes a package substrate of a rectangular shape, and a chip package including a first interface circuit die and a second interface circuit die. The first interface circuit die and second interface circuit die are mounted on a redistribution layer structure and encapsulated within a molding compound. The chip package is mounted on a top surface of the package substrate and rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through a rotation offset angle. A metal ring is mounted on the top surface of the package substrate.
    Type: Application
    Filed: December 16, 2021
    Publication date: April 7, 2022
    Applicant: MEDIATEK INC.
    Inventors: Yao-Chun Su, Chih-Jung Hsu, Yi-Jou Lin, I-Hsuan Peng
  • Publication number: 20220068930
    Abstract: A semiconductor device including a substrate, a capacitor, a stop layer, a first contact, and a second contact is provided. The substrate includes a memory array region and a peripheral circuit region. The capacitor is located in the memory array region. The capacitor includes a first electrode, a second electrode, and an insulating layer. The second electrode is located on the first electrode. The insulating layer is located between the first electrode and the second electrode. The stop layer is located on the second electrode in the memory array region and extends into the peripheral circuit region. A material of the stop layer is not a conductive material. The first contact is located in the memory array region, passes through the stop layer, and is electrically connected to the second electrode. The second contact is located in the peripheral circuit region and passes through the stop layer.
    Type: Application
    Filed: July 29, 2021
    Publication date: March 3, 2022
    Applicant: Winbond Electronics Corp.
    Inventors: Te-Hsuan Peng, Kai Jen
  • Patent number: 11264337
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a semiconductor die and a frame. The semiconductor die is disposed over the substrate. The frame is disposed over the substrate, wherein the frame is adjacent to the semiconductor die, and the upper surface of the frame is lower than the upper surface of the semiconductor die.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: March 1, 2022
    Assignee: MEDIATEK INC.
    Inventors: Chia-Cheng Chang, Tzu-Hung Lin, I-Hsuan Peng, Yi-Jou Lin
  • Publication number: 20220026861
    Abstract: A virtual metrology method using a convolutional neural network (CNN) is provided. In this method, a dynamic time warping (DTW) algorithm is used to delete unsimilar sets of process data, and adjust the sets of process data to be of the same length, thereby enabling the CNN to be used for virtual metrology. A virtual metrology model of the embodiments of the present invention includes several CNN models and a conjecture model, in which plural inputs of the CNN model are sets of time sequence data of respective parameters, and plural outputs of the CNN models are inputs to the conjecture model.
    Type: Application
    Filed: May 25, 2021
    Publication date: January 27, 2022
    Inventors: Fan-Tien CHENG, Yu-Ming HSIEH, Tan-Ju WANG, Li-Hsuan PENG, Chin-Yi LIN
  • Publication number: 20220020726
    Abstract: A semiconductor package structure includes a substrate having a substrate having a first surface and second surface opposite thereto, wherein the substrate comprises a wiring structure. The structure also has a first semiconductor die disposed on the first surface of the substrate and electrically coupled to the wiring structure, and a second semiconductor die disposed on the first surface and electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged in a side-by-side manner. A molding material surrounds the first semiconductor die and the second semiconductor die, wherein the first semiconductor die is separated from the second semiconductor die by the molding material. Finally, an annular frame mounted on the first surface of the substrate, wherein the annular frame surrounds the first semiconductor die and the second semiconductor die.
    Type: Application
    Filed: September 29, 2021
    Publication date: January 20, 2022
    Inventors: Chia-Cheng CHANG, Tzu-Hung LIN, I-Hsuan PENG, Yi-Jou LIN
  • Patent number: 11222850
    Abstract: An electronic package configured to operate at Gigabit-per-second (Gbps) data rates is disclosed. The electronic package includes a package substrate of a rectangular shape. A chip package having a first high-speed interface circuit die is mounted on a top surface of the package substrate. The chip package is rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through about 45 degrees. The first high-speed interface circuit die includes a first Serializer/Deserializer (SerDes) circuit block.
    Type: Grant
    Filed: April 12, 2020
    Date of Patent: January 11, 2022
    Assignee: MEDIATEK INC.
    Inventors: Yao-Chun Su, Chih-Jung Hsu, Yi-Jou Lin, I-Hsuan Peng
  • Patent number: 11171113
    Abstract: A semiconductor package structure includes a substrate having a first surface and second surface opposite thereto, a first semiconductor die disposed on the first surface of the substrate, a second semiconductor die disposed on the first surface, a molding material surrounding the first semiconductor die and the second semiconductor die, and an annular frame mounted on the first surface of the substrate. The first semiconductor die and the second semiconductor die are arranged in a side-by-side manner. The first semiconductor die is separated from the second semiconductor die by the molding material. The substrate includes a wiring structure. The first semiconductor die and the second semiconductor die are electrically coupled to the wiring structure. The annular frame surrounds the first semiconductor die and the second semiconductor die. The annular frame includes a retracted region at an outer corner of the annular frame.
    Type: Grant
    Filed: September 8, 2019
    Date of Patent: November 9, 2021
    Assignee: MEDIATEK INC.
    Inventors: Chia-Cheng Chang, Tzu-Hung Lin, I-Hsuan Peng, Yi-Jou Lin
  • Publication number: 20210313271
    Abstract: A semiconductor package structure includes a substrate, a first redistribution layer, a second redistribution layer, a bridge structure, a first semiconductor component, and a second semiconductor component. The first redistribution layer is over the substrate. The second redistribution layer is over the first redistribution layer. The bridge structure is between the first redistribution layer and the second redistribution layer, wherein the bridge structure includes an active device. The first semiconductor component and the second semiconductor component are located over the second redistribution layer, wherein the first semiconductor component is electrically coupled to the second semiconductor component through the second redistribution layer and the bridge structure.
    Type: Application
    Filed: March 22, 2021
    Publication date: October 7, 2021
    Inventors: Yi-Lin Tsai, Wen-Sung Hsu, I-Hsuan Peng, Yi-Jou Lin
  • Publication number: 20210313299
    Abstract: A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor component, a conductive pillar, and a second semiconductor component. The redistribution layer is over the substrate. The first semiconductor component is over the redistribution layer. The conductive pillar is adjacent to the first semiconductor component, wherein the first semiconductor component and the conductive pillar are surrounded by a molding material. The second semiconductor component is over the molding material, wherein the second semiconductor component is electrically coupled to the redistribution layer through the conductive pillar.
    Type: Application
    Filed: March 22, 2021
    Publication date: October 7, 2021
    Inventors: Yi-Lin TSAI, Wen-Sung HSU, I-Hsuan PENG, Yi-Jou LIN
  • Publication number: 20210175137
    Abstract: A semiconductor package structure including a package substrate, at least one semiconductor die, a lid structure, a first electronic component and a heat sink is provided. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is on the first surface of the package substrate and is surrounded by an encapsulating layer. The lid structure surrounds and is spaced apart from the encapsulating layer. The lid structure includes a first opening that is covered by the first surface of the package substrate. The first electronic component is over the first surface of the package substrate and arranged within the first opening of the lid structure. The heat sink covers the lid structure and the semiconductor die.
    Type: Application
    Filed: February 23, 2021
    Publication date: June 10, 2021
    Inventors: Chia-Cheng CHANG, Tzu-Hung LIN, I-Hsuan PENG, Nai-Wei LIU
  • Publication number: 20210159177
    Abstract: A semiconductor package structure includes a substrate, a bridge structure, a redistribution layer, a first semiconductor component, and a second semiconductor component. The substrate has a wiring structure. The bridge structure is over the substrate. The redistribution layer is over the bridge structure. The first semiconductor component and the second semiconductor component are over the redistribution layer, wherein the first semiconductor component is electrically coupled to the second semiconductor component through the redistribution layer and the bridge structure.
    Type: Application
    Filed: November 16, 2020
    Publication date: May 27, 2021
    Inventors: Yi-Lin TSAI, Yi-Jou LIN, I-Hsuan PENG, Wen-Sung HSU
  • Publication number: 20210111090
    Abstract: A semiconductor chip package includes a substrate having a top surface and a bottom surface, and a semiconductor device mounted on the top surface of the substrate. A gap is provided between the semiconductor device and the top surface of the substrate. A pre-cut laminate epoxy sheet is disposed on the top surface of the substrate and around a perimeter of the semiconductor device.
    Type: Application
    Filed: September 29, 2020
    Publication date: April 15, 2021
    Inventors: Yi-Lin Tsai, Yi-Jou Lin, I-Hsuan Peng, Wen-Sung Hsu
  • Patent number: 10957611
    Abstract: A semiconductor package structure including a package substrate, at least one semiconductor die, a lid structure, a first electronic component and a heat sink is provided. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is on the first surface of the package substrate and is surrounded by an encapsulating layer. The lid structure surrounds and is spaced apart from the encapsulating layer. The lid structure includes a first opening that is covered by the first surface of the package substrate. The first electronic component is over the first surface of the package substrate and arranged within the first opening of the lid structure. The heat sink covers the lid structure and the semiconductor die.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: March 23, 2021
    Assignee: MEDIATEK INC.
    Inventors: Chia-Cheng Chang, Tzu-Hung Lin, I-Hsuan Peng, Nai-Wei Liu
  • Patent number: 10920168
    Abstract: A coffee lubricant having nanoparticles is provided. It consists of 36 to 40 wt % of glycerin, 1 to 7 wt % of gum arabic, 0.3 to 1.3 wt % of nanoparticles, and remaining part of coffee biofuel. In which, the nanoparticles are CuO. The coffee biofuel is extracted from coffee dregs and has a viscosity of 60 to 70 cSt at a temperature of 40 degrees Celsius. It can reduce the friction coefficient and operating temperature. In addition, it can replace the mineral oil.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: February 16, 2021
    Assignee: NATIONAL FORMOSA UNIVERSITY
    Inventors: Jeng-Haur Horng, Chin-Chung Wei, Shin-Yuh Chern, Kuang-Hsuan Peng, Yang-Yuan Chen, Chia-Chun Yu
  • Patent number: 10903198
    Abstract: A semiconductor package assembly and method for forming the same are provided. The semiconductor package assembly includes a first semiconductor die and a second semiconductor die disposed on a first surface of a substrate. The first semiconductor die includes a peripheral region having a second edge facing the first edge of the second semiconductor die and a third edge opposite to the second edge, a circuit region surrounded by the peripheral region, wherein the circuit region has a fourth edge adjacent to the second edge and a fifth edge adjacent to the third edge. A minimum distance between the second edge and the fourth edge is a first distance, a minimum distance between the third edge and the fifth edge is a second distance, and the first distance is different from the second distance.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: January 26, 2021
    Assignee: MEDIATEK INC
    Inventors: Chia-Cheng Chang, I-Hsuan Peng, Tzu-Hung Lin