Patents by Inventor Hsueh-Hao Shih
Hsueh-Hao Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10685907Abstract: A semiconductor structure with a through silicon via includes a substrate having a front side and a back side. The through silicon via penetrates the substrate. A device is disposed on the front side of the substrate. Numerous dielectric layers cover the front side. A first test pad for testing the device is disposed on the front side of the substrate. A second test pad for testing the through silicon via is disposed on the back side of the substrate. A method of fabricating and testing the semiconductor structure is also provided.Type: GrantFiled: May 20, 2019Date of Patent: June 16, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventor: Hsueh-Hao Shih
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Publication number: 20190273033Abstract: A semiconductor structure with a through silicon via includes a substrate having a front side and a back side. The through silicon via penetrates the substrate. A device is disposed on the front side of the substrate. Numerous dielectric layers cover the front side. A first test pad for testing the device is disposed on the front side of the substrate. A second test pad for testing the through silicon via is disposed on the back side of the substrate. A method of fabricating and testing the semiconductor structure is also provided.Type: ApplicationFiled: May 20, 2019Publication date: September 5, 2019Inventor: Hsueh-Hao Shih
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Patent number: 10340203Abstract: A semiconductor structure with a through silicon via includes a substrate having a front side and a back side. The through silicon via penetrates the substrate. A device is disposed on the front side of the substrate. Numerous dielectric layers cover the front side. A first test pad for testing the device is disposed on the front side of the substrate. A second test pad for testing the through silicon via is disposed on the back side of the substrate. A method of fabricating and testing the semiconductor structure is also provided.Type: GrantFiled: February 7, 2014Date of Patent: July 2, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventor: Hsueh-Hao Shih
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Publication number: 20180286872Abstract: A semiconductor memory device having a memory cell including a plurality of memory cells, a first P-type well region, a second P-type well region, and an N-type well region disposed between the first P-Type well region and the second P-type well region. The semiconductor memory element defines a plurality of first regions, a plurality of second regions, a plurality of third regions, and a plurality of fourth regions, and each first region includes the memory cell. Each second region, each third region and each fourth region include a voltage contact to provide a voltage to the first P-type well region, the second P-type well region, and the N-type well region. The first region to the fourth region do not overlap with each other.Type: ApplicationFiled: April 26, 2017Publication date: October 4, 2018Inventors: Chien-Hung Chen, Meng-Ping Chuang, Hsueh-Hao Shih
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Patent number: 10090308Abstract: A semiconductor memory device having a memory cell including a plurality of memory cells, a first P-type well region, a second P-type well region, and an N-type well region disposed between the first P-Type well region and the second P-type well region. The semiconductor memory element defines a plurality of first regions, a plurality of second regions, a plurality of third regions, and a plurality of fourth regions, and each first region includes the memory cell. Each second region, each third region and each fourth region include a voltage contact to provide a voltage to the first P-type well region, the second P-type well region, and the N-type well region. The first region to the fourth region do not overlap with each other.Type: GrantFiled: April 26, 2017Date of Patent: October 2, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chien-Hung Chen, Meng-Ping Chuang, Hsueh-Hao Shih
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Patent number: 9653546Abstract: A manufacturing method of a nanowire structure includes the following steps. A fin and a shallow trench isolation (STI) are formed on a substrate. A first patterned insulation layer is formed on an exposed upper part of the fin. The STI is then recessed for exposing a lower part of the fin. A second patterned insulation layer is formed in second regions for covering the first patterned insulation layer and the exposed part of the fin. The lower part of the fin is then removed for forming an upper fin and a lower fin in a first region. The STI is further recessed for exposing a portion of the lower fin and a portion of the fin in the second regions. The first patterned insulation layer on the first region is removed, and the upper fin is converted into a first nanowire.Type: GrantFiled: April 16, 2015Date of Patent: May 16, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventor: Hsueh-Hao Shih
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Publication number: 20160268376Abstract: A manufacturing method of a nanowire structure includes the following steps. A fin and a shallow trench isolation (STI) are formed on a substrate. A first patterned insulation layer is formed on an exposed upper part of the fin. The STI is then recessed for exposing a lower part of the fin. A second patterned insulation layer is formed in second regions for covering the first patterned insulation layer and the exposed part of the fin. The lower part of the fin is then removed for forming an upper fin and a lower fin in a first region. The STI is further recessed for exposing a portion of the lower fin and a portion of the fin in the second regions. The first patterned insulation layer on the first region is removed, and the upper fin is converted into a first nanowire.Type: ApplicationFiled: April 16, 2015Publication date: September 15, 2016Inventor: Hsueh-Hao Shih
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Patent number: 9177909Abstract: A semiconductor capacitor is includes a substrate, a plurality of odd layers formed on the substrate, and a plurality of even layers formed on the substrate. Each odd layer includes a plurality of first odd fingers and a first odd terminal electrically connected thereto, and a plurality of second odd fingers and a second odd terminal electrically connected thereto. Each even layer includes a plurality of first even fingers and a first even terminal electrically connected thereto, and a plurality of second even fingers and a second even terminal electrically connected thereto. The semiconductor capacitor further includes at least a first odd connecting structure electrically connecting the first odd terminals, at least a second odd connecting structure electrically connecting the second odd terminals, at least a first even connecting structure electrically connecting the first even terminals, and at least a second even connecting structure electrically connecting the second even terminals.Type: GrantFiled: August 14, 2013Date of Patent: November 3, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventor: Hsueh-Hao Shih
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Publication number: 20150228547Abstract: A semiconductor structure with a through silicon via includes a substrate having a front side and a back side. The through silicon via penetrates the substrate. A device is disposed on the front side of the substrate. Numerous dielectric layers cover the front side. A first test pad for testing the device is disposed on the front side of the substrate. A second test pad for testing the through silicon via is disposed on the back side of the substrate. A method of fabricating and testing the semiconductor structure is also provided.Type: ApplicationFiled: February 7, 2014Publication date: August 13, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventor: Hsueh-Hao Shih
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Publication number: 20150048482Abstract: A semiconductor capacitor is includes a substrate, a plurality of odd layers formed on the substrate, and a plurality of even layers formed on the substrate. Each odd layer includes a plurality of first odd fingers and a first odd terminal electrically connected thereto, and a plurality of second odd fingers and a second odd terminal electrically connected thereto. Each even layer includes a plurality of first even fingers and a first even terminal electrically connected thereto, and a plurality of second even fingers and a second even terminal electrically connected thereto. The semiconductor capacitor further includes at least a first odd connecting structure electrically connecting the first odd terminals, at least a second odd connecting structure electrically connecting the second odd terminals, at least a first even connecting structure electrically connecting the first even terminals, and at least a second even connecting structure electrically connecting the second even terminals.Type: ApplicationFiled: August 14, 2013Publication date: February 19, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventor: Hsueh-Hao Shih
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Patent number: 7314796Abstract: The present invention is directed to forming memory wordlines having a relatively lower sheet resistance. In one embodiment, a control-gate poly layer including a first and a second poly-Si portion is deposited. a The first poly-Si portion is deposited on a semiconductor substrate using a first precursor gas flow rate. A The second poly-Si portion is deposited on the first poly-Si portion using a second precursor gas flow rate, where the second precursor flow rate higher than the first precursor gas flow rate. A tungsten silicide layer is then deposited. A wordline is formed from a stacked film of the control-gate poly layer and tungsten silicide layer. The control-gate poly layer and tungsten silicide layer are then patterned to form a gate electrode, and a implantation process is made, after or before, forming the tungsten silicide layer.Type: GrantFiled: December 17, 2004Date of Patent: January 1, 2008Assignee: Macronix International Co., Ltd.Inventors: Hung-Wei Liu, Hsueh-Hao Shih, Szu-Yu Wang
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Publication number: 20060134863Abstract: The present invention is directed to forming memory wordlines having a relatively lower sheet resistance. In one embodiment, a first poly-Si portion is deposited on a semiconductor substrate using a first precursor gas flow rate. A second poly-Si portion is deposited using a second precursor gas flow rate, where the second precursor flow rate higher than the first precursor gas flow rate. A tungsten silicide layer is deposited using silane gas. Wordlines are formed in trenches from poly-Si and WSix. A gate electrode is implanted.Type: ApplicationFiled: December 17, 2004Publication date: June 22, 2006Inventors: Hung-Wei Liu, Hsueh-Hao Shih, Szu-Yu Wang
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Patent number: 6911374Abstract: A fabrication method for a shallow trench isolation region is described. A part of the trench is filled with a first insulation layer, followed by performing a surface treatment process to form a surface treated layer on the surface of a part of the first insulation layer. The surface treated layer is then removed, followed by forming a second insulation layer on the first insulation layer and filling the trench to form a shallow trench isolation region. Since a part of the trench is first filled with the first insulation layer, followed by removing a portion of the first insulation layer, the aspect ratio of the trench is lower before the filling of the second insulation in the trench. The adverse result, such as, void formation in the shallow trench isolation region due to a high aspect ratio, is thus prevented.Type: GrantFiled: August 5, 2003Date of Patent: June 28, 2005Assignee: Macronix International Co., Ltd.Inventors: Chin Hsiang Lin, Chin-Wei Liao, Hsueh-Hao Shih, Kuang-Chao Chen
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Patent number: 6887757Abstract: A method of fabricating a flash memory device is provided. First, a substrate partitioned into a memory cell region and a peripheral circuit region is provided. A tunnel dielectric layer is formed over the memory cell region and a liner layer is formed over the peripheral circuit region. Thereafter, a patterned gate conductive layer is formed over the substrate. An inter-gate dielectric layer and a passivation layer are sequentially formed over the substrate. The passivation layer, the inter-gate dielectric layer, the gate conductive layer and the liner layer over the peripheral circuit region are removed. A gate dielectric layer is formed over the peripheral circuit region while the passivation layer over the memory cell region is converted into an oxide layer. Another conductive layer is formed over the substrate. The conductive layer, the oxide layer, the inter-gate dielectric layer and the gate conductive layer over the memory cell region are patterned to form a memory gate.Type: GrantFiled: May 14, 2003Date of Patent: May 3, 2005Assignee: MACRONIX International Co., Ltd.Inventors: Kuang-Chao Chen, Hsueh-Hao Shih, Ling-Wuu Yang
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Publication number: 20050084990Abstract: A method of manufacturing a semiconductor device that comprises the steps of providing a semiconductor wafer including a patterned layer, forming a first insulating layer over the patterned layer of the semiconductor wafer, the first insulating layer including a first index of refraction, forming a second insulating layer over the first insulating layer, the second insulating layer including a second index of refraction smaller than the first index of refraction, removing the second insulating layer by a planarizing process, and detecting a change in index of refraction during the planarizing process.Type: ApplicationFiled: October 16, 2003Publication date: April 21, 2005Inventors: Yuh-Turng Liu, Kuang-Chao Chen, Hsueh-Hao Shih, Yun-Chi Yang, Yung-Tai Hung
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Publication number: 20050009337Abstract: A method of forming a suicide layer is described. A silicon layer is provided. Ions are introduced in the silicon layer. A metal layer is formed on the silicon layer. An annealing process is performed so that the silicon layer reacts with the metal layer to form the metal silicide layer. Thereafter, the unreacted metal layer is removed. The uniformity of the grain size and the grain distribution of the metal silicide layer are improved by introducing the ions in the silicon layer before performing the annealing process, so that sheet resistance of the metal silicide layer is reduced.Type: ApplicationFiled: August 21, 2003Publication date: January 13, 2005Inventors: Hung-Wei Liu, Kuang-Chao Chen, Hsueh-Hao Shih
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Publication number: 20040259480Abstract: A chemical mechanical polishing to polish a substrate having a layer to be polished thereon is described. A pre-polishing process is performed using a softer polishing pad to remove partially raised parts of the layer to be polished before conducting a polishing process using a harder polishing pad. Since the first polishing pad is flexible, porous and with low density, the first polishing pad can be deformed to increase contact areas between the first polishing pad and the raised part of the layer to be polished, and the abrasives are embedded easily in holes of the surface of the first polishing pad. Ultimately, the layer to be polished can be polished directly during the pre-polishing process. Therefore, the processing time is reduced, the consumption of the slurry is decreased and the process cost can be cut down substantially.Type: ApplicationFiled: September 30, 2003Publication date: December 23, 2004Inventors: YUNG-TAI HUNG, YUHTURNG LIU, HSUEH-HAO SHIH, KUANG-CHAO CHEN
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Patent number: 6824452Abstract: A chemical mechanical polishing to polish a substrate having a layer to be polished thereon is described. A pre-polishing process is performed using a softer polishing pad to remove partially raised parts of the layer to be polished before conducting a polishing process using a harder polishing pad. Since the first polishing pad is flexible, porous and with low density, the first polishing pad can be deformed to increase contact areas between the first polishing pad and the raised part of the layer to be polished, and the abrasives are embedded easily in holes of the surface of the first polishing pad. Ultimately, the layer to be polished can be polished directly during the pre-polishing process. Therefore, the processing time is reduced, the consumption of the slurry is decreased and the process cost can be cut down substantially.Type: GrantFiled: September 30, 2003Date of Patent: November 30, 2004Assignee: Macronix International Co., Ltd.Inventors: Yung-Tai Hung, Yuhturng Liu, Hsueh-Hao Shih, Kuang-Chao Chen
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Publication number: 20040229435Abstract: A method of fabricating a flash memory device is provided. First, a substrate partitioned into a memory cell region and a peripheral circuit region is provided. A tunnel dielectric layer is formed over the memory cell region and a liner layer is formed over the peripheral circuit region. Thereafter, a patterned gate conductive layer is formed over the substrate. An inter-gate dielectric layer and a passivation layer are sequentially formed over the substrate. The passivation layer, the inter-gate dielectric layer, the gate conductive layer and the liner layer over the peripheral circuit region are removed. A gate dielectric layer is formed over the peripheral circuit region while the passivation layer over the memory cell region is converted into an oxide layer. Another conductive layer is formed over the substrate. The conductive layer, the oxide layer, the inter-gate dielectric layer and the gate conductive layer over the memory cell region are patterned to form a memory gate.Type: ApplicationFiled: May 14, 2003Publication date: November 18, 2004Inventors: Kuang-Chao Chen, Hsueh-Hao Shih, Ling-Wuu Yang
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Patent number: RE40113Abstract: A method for fabricating gate oxide includes a dilute wet oxidation process with additional nitrogen and moisture and an annealing process with a nitrogen base gas, wherein the volume of additional nitrogen is about 6-12 6-20 times of the volume of the additional moisture. The method according to the invention improves the electrical quality of the gate oxide by raising the Qbd and by reducing the leakage current of the gate oxide.Type: GrantFiled: September 17, 2002Date of Patent: February 26, 2008Assignee: United Microelectronics Corp.Inventors: Yu-Shan Tai, H. T. Yang, Hsueh-Hao Shih, Kuen-Chu Chen