Patents by Inventor Hsueh Kuo Liao

Hsueh Kuo Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6919628
    Abstract: A stack chip package structure is provided. One principal feature of the structure is the formation of a few peripheral surfaces (e.g. ladder or lead-angle surfaces) at the bottom peripheral sections of a stack structure. When the stack structure is attached to a surface of a die through an adhesive layer, the thickness of the adhesive layer under a peripheral section of the stack structure is greater than a central region. Therefore, as the chip package is subjected to a thermal stress test, the adhesive layer under the peripheral sections of the stack structure is able to provide some buffering against thermal stress so that the stress concentration around the stack structure is reduced. Consequently, damages of the die surface due to stress are prevented and the average working life of the chip package is extended.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: July 19, 2005
    Assignee: Via Technologies, Inc.
    Inventors: I-Tseng Lee, Hsueh Kuo Liao, Jen-Te Tseng
  • Publication number: 20040140546
    Abstract: A stack chip package structure is provided. One principal feature of the structure is the formation of a few peripheral surfaces (e.g. ladder or lead-angle surfaces) at the bottom peripheral sections of a stack structure. When the stack structure is attached to a surface of a die through an adhesive layer, the thickness of the adhesive layer under a peripheral section of the stack structure is greater than a central region. Therefore, as the chip package is subjected to a thermal stress test, the adhesive layer under the peripheral sections of the stack structure is able to provide some buffering against thermal stress so that the stress concentration around the stack structure is reduced. Consequently, damages of the die surface due to stress are prevented and the average working life of the chip package is extended.
    Type: Application
    Filed: July 18, 2003
    Publication date: July 22, 2004
    Inventors: I-TSENG LEE, HSUEH KUO LIAO, JEN-TE TSENG
  • Publication number: 20040094826
    Abstract: A leadframe packaging apparatus including a die, at least two separated die pads each connected to a corresponding voltage level thereof, a plurality of leadfingers, and at least one passive component having two ends each connected to one of the two separated die pads. A packaging method for the leadframe apparatus is further provided, wherein the method prepares at least one die pad disposed in separated fashion, integrated circuit dies adhered to separated die pads, and passive components having two ends connected with separated die pads before forming the molding compound, thereby placing the passive components within the molding compound.
    Type: Application
    Filed: July 3, 2003
    Publication date: May 20, 2004
    Inventors: Chin An Yang, Hsueh Kuo Liao