Patents by Inventor Hsueh-Wei Chen

Hsueh-Wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240160303
    Abstract: A control method of a touchpad is provided. The touchpad has a determination module including a neural network. The determination module is used to determine the type of object. When the user uses the touchpad, the touchpad uses the captured object feature data of the touch object to update the determination module. Therefore, when determining the type of the touch object, the updated determination module can more accurately determine the touch object used by the user, so as to improve the determination accuracy.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 16, 2024
    Applicant: ELAN MICROELECTRONICS CORPORATION
    Inventors: Chang-Ru CHEN, Tuan-Ying CHANG, Hsueh-Wei YANG
  • Publication number: 20240161833
    Abstract: A memory cell is connected to a source line, a bit line, a word line, an assist gate line and an erase line. When a program action is performed, a weak programming procedure is first performed on the memory cell, and then a strong programming procedure is performed on the memory cell. When the weak programming procedure is performed, an on voltage is provided to the word line, a first program voltage is provided to the source line, a ground voltage is provided to the bit line, a first assist gate voltage is provided to the assist gate line, and a first erase line voltage is provided to the erase line. When the strong programming procedure is performed, a lower program voltage and a higher assist gate voltage are provided to the memory cell.
    Type: Application
    Filed: November 7, 2023
    Publication date: May 16, 2024
    Inventors: Hsueh-Wei CHEN, Wei-Chiang ONG
  • Patent number: 11980029
    Abstract: An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. The memory cell comprises a select transistor and a floating gate transistor. The floating gate of the floating gate transistor and an assist gate region are collaboratively formed as a capacitor. The floating gate of the floating gate transistor and an erase gate region are collaboratively formed as another capacitor. Moreover, the select transistor, the floating gate transistor and the two capacitors are collaboratively formed as a four-terminal memory cell. Consequently, the size of the memory cell is small, and the memory cell is operated more easily.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: May 7, 2024
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Hsueh-Wei Chen
  • Publication number: 20240071767
    Abstract: A method includes removing a dummy gate stack to form a trench between gate spacers, depositing a gate dielectric extending into the trench, and performing a first treatment process on the gate dielectric. The first treatment process is performed using a fluorine-containing gas. A first drive-in process is then performed to drive fluorine in the fluorine-containing gas into the gate dielectric. The method further includes performing a second treatment process on the gate dielectric, wherein the second treatment process is performed using the fluorine-containing gas, and performing a second drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric. After the second drive-in process, conductive layers are formed to fill the trench.
    Type: Application
    Filed: January 6, 2023
    Publication date: February 29, 2024
    Inventors: Hsueh-Ju Chen, Chi On Chui, Tsung-Da Lin, Pei Ying Lai, Chia-Wei Hsu
  • Patent number: 11877456
    Abstract: A memory cell of a non-volatile memory includes a memory element. The memory element is a transistor. The memory element includes an asymmetric spacer. In the memory element, a channel under the wider part of the spacer is longer. When the program operation of the memory element is performed, more carriers are injected into a charge-trapping layer of the spacer through the longer channel. Consequently, the program operation of the memory element is performed more efficiently, and the time period of performing the program operation is reduced.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: January 16, 2024
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Ying-Je Chen, Wein-Town Sun, Chun-Hsiao Li, Hsueh-Wei Chen
  • Patent number: 11818887
    Abstract: An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. In the memory cell of the array structure, the assist gate region is composed at least two plate capacitors. Especially, the assist gate region at least contains a poly/poly plate capacitor and a metal/poly plate capacitor. The structures and the fabricating processes of the plate capacitors are simple. In addition, the uses of the plate capacitors can effectively reduce the size of the memory cell.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: November 14, 2023
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Hsueh-Wei Chen, Woan-Yun Hsiao, Wei-Ren Chen, Wein-Town Sun
  • Publication number: 20230328978
    Abstract: A non-volatile memory cell includes a p-type well region, a first n-type doped region, a second n-type doped region, a first gate structure, a second gate structure, a third gate structure and a protecting layer. The first n-type doped region and the second n-type doped region are formed under a surface of the p-type well region. The first gate structure and the second gate structure are formed over the surface of the p-type well region and arranged between the first n-type doped region and the second n-type doped region. A first part of a first gate layer of the first gate structure and the second gate structure are covered by the protecting layer. The third gate structure is formed over the surface of the p-type well region and arranged between the first gate structure and the second gate structure.
    Type: Application
    Filed: March 27, 2023
    Publication date: October 12, 2023
    Inventors: Wein-Town SUN, Woan-Yun HSIAO, Wei-Ren CHEN, Hsueh-Wei CHEN
  • Patent number: 11663455
    Abstract: A resistive random-access memory cell includes a well region, a first doped region, a second doped region, a third doped region, a first gate structure, a second gate structure and a third gate structure. The first gate structure is formed over the surface of the well region between the first doped region and the second doped region. The second gate structure is formed over the second doped region. The third gate structure is formed over the surface of the well region between the second doped region and the third doped region. A first metal layer is connected with the first doped region and the third doped region. A second metal layer is connected with the conductive layer of the first gate structure and the conductive layer of the third gate structure.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: May 30, 2023
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Tsung-Mu Lai, Wei-Chen Chang, Hsueh-Wei Chen
  • Publication number: 20230157017
    Abstract: An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. The memory cell comprises a select transistor and a floating gate transistor. The floating gate of the floating gate transistor and an assist gate region are collaboratively formed as a capacitor. The floating gate of the floating gate transistor and an erase gate region are collaboratively formed as another capacitor. Moreover, the select transistor, the floating gate transistor and the two capacitors are collaboratively formed as a four-terminal memory cell. Consequently, the size of the memory cell is small, and the memory cell is operated more easily.
    Type: Application
    Filed: August 9, 2022
    Publication date: May 18, 2023
    Inventor: Hsueh-Wei CHEN
  • Publication number: 20230119398
    Abstract: An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. In the memory cell of the array structure, the assist gate region is composed at least two plate capacitors. Especially, the assist gate region at least contains a poly/poly plate capacitor and a metal/poly plate capacitor. The structures and the fabricating processes of the plate capacitors are simple. In addition, the uses of the plate capacitors can effectively reduce the size of the memory cell.
    Type: Application
    Filed: March 4, 2022
    Publication date: April 20, 2023
    Inventors: Hsueh-Wei CHEN, Woan-Yun HSIAO, Wei-Ren CHEN, Wein-Town SUN
  • Publication number: 20220085038
    Abstract: A memory cell of a non-volatile memory includes a memory element. The memory element is a transistor. The memory element includes an asymmetric spacer. In the memory element, a channel under the wider part of the spacer is longer. When the program operation of the memory element is performed, more carriers are injected into a charge-trapping layer of the spacer through the longer channel. Consequently, the program operation of the memory element is performed more efficiently, and the time period of performing the program operation is reduced.
    Type: Application
    Filed: July 21, 2021
    Publication date: March 17, 2022
    Inventors: Ying-Je CHEN, Wein-Town SUN, Chun-Hsiao LI, Hsueh-Wei CHEN
  • Patent number: 11245004
    Abstract: A non-volatile memory includes a substrate region, a barrier layer, an N-type well region, an isolation structure, a first gate structure, a first sidewall insulator, a first P-type doped region, a second P-type doped region and an N-type doped region. The isolation structure is arranged around the N-type well region and formed over the barrier layer. The N-type well region is surrounded by the isolation structure and the barrier layer. Consequently, the N-type well region is an isolation well region. The first gate structure is formed over a surface of the N-type well region. The first sidewall insulator is arranged around the first gate structure. The first P-type doped region, the second P-type doped region and the N-type doped region are formed under the surface of the N-type well region.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: February 8, 2022
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Hsueh-Wei Chen, Wei-Ren Chen, Wein-Town Sun
  • Publication number: 20210249601
    Abstract: A resistive random-access memory cell includes a well region, a first doped region, a second doped region, a third doped region, a first gate structure, a second gate structure and a third gate structure. The first gate structure is formed over the surface of the well region between the first doped region and the second doped region. The second gate structure is formed over the second doped region. The third gate structure is formed over the surface of the well region between the second doped region and the third doped region. A first metal layer is connected with the first doped region and the third doped region. A second metal layer is connected with the conductive layer of the first gate structure and the conductive layer of the third gate structure.
    Type: Application
    Filed: November 24, 2020
    Publication date: August 12, 2021
    Inventors: Tsung-Mu LAI, Wei-Chen CHANG, Hsueh-Wei CHEN
  • Patent number: 11049564
    Abstract: An erasable programmable non-volatile memory includes a memory array and a sensing circuit. The memory array includes a general memory cell and a reference memory cell, which are connected with a word line. The sensing circuit includes a current comparator. The read current in the program state of the general memory cell is higher than the read current in the program state of the reference memory cell. The erase efficiency of the general memory cell is higher than the erase efficiency of the reference memory cell. When a read action is performed, the general memory cell generates a read current to the current comparator, and the reference memory cell generates a reference current to the current comparator. According to the reference current and the read current, the current comparator generates an output data signal to indicate a storage state of the general memory cell.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: June 29, 2021
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Wein-Town Sun, Hsueh-Wei Chen, Chun-Hsiao Li, Wei-Ren Chen, Hong-Yi Liao
  • Publication number: 20210183998
    Abstract: A non-volatile memory includes a substrate region, a barrier layer, an N-type well region, an isolation structure, a first gate structure, a first sidewall insulator, a first P-type doped region, a second P-type doped region and an N-type doped region. The isolation structure is arranged around the N-type well region and formed over the barrier layer. The N-type well region is surrounded by the isolation structure and the barrier layer. Consequently, the N-type well region is an isolation well region. The first gate structure is formed over a surface of the N-type well region. The first sidewall insulator is arranged around the first gate structure. The first P-type doped region, the second P-type doped region and the N-type doped region are formed under the surface of the N-type well region.
    Type: Application
    Filed: September 30, 2020
    Publication date: June 17, 2021
    Inventors: Hsueh-Wei CHEN, Wei-Ren CHEN, Wein-Town SUN
  • Patent number: 10797063
    Abstract: A single-poly non-volatile memory unit includes: a semiconductor substrate having a first conductivity type; first, second and third OD regions disposed on the semiconductor substrate and separated from each other by an isolation region, wherein the first OD region and the second OD region are formed in a first ion well, and the first ion well has a second conductivity type; a first memory cell disposed on the first OD region, a second memory cell disposed on the second OD region. The first memory cell and the second memory cell exhibit an asymmetric memory cell layout structure with respect to an axis. An erase gate is disposed in the third OD region.
    Type: Grant
    Filed: December 25, 2018
    Date of Patent: October 6, 2020
    Assignee: eMemory Technology Inc.
    Inventors: Hsueh-Wei Chen, Wei-Ren Chen, Wein-Town Sun, Jui-Ming Kuo
  • Publication number: 20200294593
    Abstract: An erasable programmable non-volatile memory includes a memory array and a sensing circuit. The memory array includes a general memory cell and a reference memory cell, which are connected with a word line. The sensing circuit includes a current comparator. The read current in the program state of the general memory cell is higher than the read current in the program state of the reference memory cell. The erase efficiency of the general memory cell is higher than the erase efficiency of the reference memory cell. When a read action is performed, the general memory cell generates a read current to the current comparator, and the reference memory cell generates a reference current to the current comparator. According to the reference current and the read current, the current comparator generates an output data signal to indicate a storage state of the general memory cell.
    Type: Application
    Filed: February 27, 2020
    Publication date: September 17, 2020
    Inventors: Wein-Town SUN, Hsueh-Wei CHEN, Chun-Hsiao LI, Wei-Ren CHEN, Hong-Yi LIAO
  • Publication number: 20190214401
    Abstract: A single-poly non-volatile memory unit includes: a semiconductor substrate having a first conductivity type; first, second and third OD regions disposed on the semiconductor substrate and separated from each other by an isolation region, wherein the first OD region and the second OD region are formed in a first ion well, and the first ion well has a second conductivity type; a first memory cell disposed on the first OD region, a second memory cell disposed on the second OD region. The first memory cell and the second memory cell exhibit an asymmetric memory cell layout structure with respect to an axis. An erase gate is disposed in the third OD region.
    Type: Application
    Filed: December 25, 2018
    Publication date: July 11, 2019
    Inventors: Hsueh-Wei Chen, Wei-Ren Chen, Wein-Town Sun, Jui-Ming Kuo
  • Patent number: 10115682
    Abstract: An erasable programmable non-volatile memory includes a first transistor, a second transistor, an erase gate region and a metal layer. The first transistor includes a select gate, a first doped region and a second doped region. The select gate is connected with a word line. The first doped region is connected with a source line. The second transistor includes the second doped region, a third doped region and a floating gate. The third doped region is connected with a bit line. The erase gate region is connected with an erase line. The floating gate is extended over the erase gate region and located near the erase gate region. The metal layer is disposed over the floating gate and connected with the bit line.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: October 30, 2018
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Chun-Hsiao Li, Wei-Ren Chen, Hsueh-Wei Chen
  • Patent number: D1016792
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: March 5, 2024
    Assignee: Acer Incorporated
    Inventors: Hsueh-Wei Chung, Pao-Ching Huang, Kai-Teng Cheng, Hung-Chi Chen