Patents by Inventor Hsueh-Wei Chen
Hsueh-Wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11980029Abstract: An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. The memory cell comprises a select transistor and a floating gate transistor. The floating gate of the floating gate transistor and an assist gate region are collaboratively formed as a capacitor. The floating gate of the floating gate transistor and an erase gate region are collaboratively formed as another capacitor. Moreover, the select transistor, the floating gate transistor and the two capacitors are collaboratively formed as a four-terminal memory cell. Consequently, the size of the memory cell is small, and the memory cell is operated more easily.Type: GrantFiled: August 9, 2022Date of Patent: May 7, 2024Assignee: EMEMORY TECHNOLOGY INC.Inventor: Hsueh-Wei Chen
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Publication number: 20240071767Abstract: A method includes removing a dummy gate stack to form a trench between gate spacers, depositing a gate dielectric extending into the trench, and performing a first treatment process on the gate dielectric. The first treatment process is performed using a fluorine-containing gas. A first drive-in process is then performed to drive fluorine in the fluorine-containing gas into the gate dielectric. The method further includes performing a second treatment process on the gate dielectric, wherein the second treatment process is performed using the fluorine-containing gas, and performing a second drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric. After the second drive-in process, conductive layers are formed to fill the trench.Type: ApplicationFiled: January 6, 2023Publication date: February 29, 2024Inventors: Hsueh-Ju Chen, Chi On Chui, Tsung-Da Lin, Pei Ying Lai, Chia-Wei Hsu
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Patent number: 11877456Abstract: A memory cell of a non-volatile memory includes a memory element. The memory element is a transistor. The memory element includes an asymmetric spacer. In the memory element, a channel under the wider part of the spacer is longer. When the program operation of the memory element is performed, more carriers are injected into a charge-trapping layer of the spacer through the longer channel. Consequently, the program operation of the memory element is performed more efficiently, and the time period of performing the program operation is reduced.Type: GrantFiled: July 21, 2021Date of Patent: January 16, 2024Assignee: EMEMORY TECHNOLOGY INC.Inventors: Ying-Je Chen, Wein-Town Sun, Chun-Hsiao Li, Hsueh-Wei Chen
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Patent number: 11818887Abstract: An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. In the memory cell of the array structure, the assist gate region is composed at least two plate capacitors. Especially, the assist gate region at least contains a poly/poly plate capacitor and a metal/poly plate capacitor. The structures and the fabricating processes of the plate capacitors are simple. In addition, the uses of the plate capacitors can effectively reduce the size of the memory cell.Type: GrantFiled: March 4, 2022Date of Patent: November 14, 2023Assignee: EMEMORY TECHNOLOGY INC.Inventors: Hsueh-Wei Chen, Woan-Yun Hsiao, Wei-Ren Chen, Wein-Town Sun
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Publication number: 20230328978Abstract: A non-volatile memory cell includes a p-type well region, a first n-type doped region, a second n-type doped region, a first gate structure, a second gate structure, a third gate structure and a protecting layer. The first n-type doped region and the second n-type doped region are formed under a surface of the p-type well region. The first gate structure and the second gate structure are formed over the surface of the p-type well region and arranged between the first n-type doped region and the second n-type doped region. A first part of a first gate layer of the first gate structure and the second gate structure are covered by the protecting layer. The third gate structure is formed over the surface of the p-type well region and arranged between the first gate structure and the second gate structure.Type: ApplicationFiled: March 27, 2023Publication date: October 12, 2023Inventors: Wein-Town SUN, Woan-Yun HSIAO, Wei-Ren CHEN, Hsueh-Wei CHEN
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Patent number: 11663455Abstract: A resistive random-access memory cell includes a well region, a first doped region, a second doped region, a third doped region, a first gate structure, a second gate structure and a third gate structure. The first gate structure is formed over the surface of the well region between the first doped region and the second doped region. The second gate structure is formed over the second doped region. The third gate structure is formed over the surface of the well region between the second doped region and the third doped region. A first metal layer is connected with the first doped region and the third doped region. A second metal layer is connected with the conductive layer of the first gate structure and the conductive layer of the third gate structure.Type: GrantFiled: November 24, 2020Date of Patent: May 30, 2023Assignee: EMEMORY TECHNOLOGY INC.Inventors: Tsung-Mu Lai, Wei-Chen Chang, Hsueh-Wei Chen
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Publication number: 20230157017Abstract: An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. The memory cell comprises a select transistor and a floating gate transistor. The floating gate of the floating gate transistor and an assist gate region are collaboratively formed as a capacitor. The floating gate of the floating gate transistor and an erase gate region are collaboratively formed as another capacitor. Moreover, the select transistor, the floating gate transistor and the two capacitors are collaboratively formed as a four-terminal memory cell. Consequently, the size of the memory cell is small, and the memory cell is operated more easily.Type: ApplicationFiled: August 9, 2022Publication date: May 18, 2023Inventor: Hsueh-Wei CHEN
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Publication number: 20230119398Abstract: An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. In the memory cell of the array structure, the assist gate region is composed at least two plate capacitors. Especially, the assist gate region at least contains a poly/poly plate capacitor and a metal/poly plate capacitor. The structures and the fabricating processes of the plate capacitors are simple. In addition, the uses of the plate capacitors can effectively reduce the size of the memory cell.Type: ApplicationFiled: March 4, 2022Publication date: April 20, 2023Inventors: Hsueh-Wei CHEN, Woan-Yun HSIAO, Wei-Ren CHEN, Wein-Town SUN
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Publication number: 20220085038Abstract: A memory cell of a non-volatile memory includes a memory element. The memory element is a transistor. The memory element includes an asymmetric spacer. In the memory element, a channel under the wider part of the spacer is longer. When the program operation of the memory element is performed, more carriers are injected into a charge-trapping layer of the spacer through the longer channel. Consequently, the program operation of the memory element is performed more efficiently, and the time period of performing the program operation is reduced.Type: ApplicationFiled: July 21, 2021Publication date: March 17, 2022Inventors: Ying-Je CHEN, Wein-Town SUN, Chun-Hsiao LI, Hsueh-Wei CHEN
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Patent number: 11245004Abstract: A non-volatile memory includes a substrate region, a barrier layer, an N-type well region, an isolation structure, a first gate structure, a first sidewall insulator, a first P-type doped region, a second P-type doped region and an N-type doped region. The isolation structure is arranged around the N-type well region and formed over the barrier layer. The N-type well region is surrounded by the isolation structure and the barrier layer. Consequently, the N-type well region is an isolation well region. The first gate structure is formed over a surface of the N-type well region. The first sidewall insulator is arranged around the first gate structure. The first P-type doped region, the second P-type doped region and the N-type doped region are formed under the surface of the N-type well region.Type: GrantFiled: September 30, 2020Date of Patent: February 8, 2022Assignee: EMEMORY TECHNOLOGY INC.Inventors: Hsueh-Wei Chen, Wei-Ren Chen, Wein-Town Sun
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Publication number: 20210249601Abstract: A resistive random-access memory cell includes a well region, a first doped region, a second doped region, a third doped region, a first gate structure, a second gate structure and a third gate structure. The first gate structure is formed over the surface of the well region between the first doped region and the second doped region. The second gate structure is formed over the second doped region. The third gate structure is formed over the surface of the well region between the second doped region and the third doped region. A first metal layer is connected with the first doped region and the third doped region. A second metal layer is connected with the conductive layer of the first gate structure and the conductive layer of the third gate structure.Type: ApplicationFiled: November 24, 2020Publication date: August 12, 2021Inventors: Tsung-Mu LAI, Wei-Chen CHANG, Hsueh-Wei CHEN
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Patent number: 11049564Abstract: An erasable programmable non-volatile memory includes a memory array and a sensing circuit. The memory array includes a general memory cell and a reference memory cell, which are connected with a word line. The sensing circuit includes a current comparator. The read current in the program state of the general memory cell is higher than the read current in the program state of the reference memory cell. The erase efficiency of the general memory cell is higher than the erase efficiency of the reference memory cell. When a read action is performed, the general memory cell generates a read current to the current comparator, and the reference memory cell generates a reference current to the current comparator. According to the reference current and the read current, the current comparator generates an output data signal to indicate a storage state of the general memory cell.Type: GrantFiled: February 27, 2020Date of Patent: June 29, 2021Assignee: EMEMORY TECHNOLOGY INC.Inventors: Wein-Town Sun, Hsueh-Wei Chen, Chun-Hsiao Li, Wei-Ren Chen, Hong-Yi Liao
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Publication number: 20210183998Abstract: A non-volatile memory includes a substrate region, a barrier layer, an N-type well region, an isolation structure, a first gate structure, a first sidewall insulator, a first P-type doped region, a second P-type doped region and an N-type doped region. The isolation structure is arranged around the N-type well region and formed over the barrier layer. The N-type well region is surrounded by the isolation structure and the barrier layer. Consequently, the N-type well region is an isolation well region. The first gate structure is formed over a surface of the N-type well region. The first sidewall insulator is arranged around the first gate structure. The first P-type doped region, the second P-type doped region and the N-type doped region are formed under the surface of the N-type well region.Type: ApplicationFiled: September 30, 2020Publication date: June 17, 2021Inventors: Hsueh-Wei CHEN, Wei-Ren CHEN, Wein-Town SUN
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Patent number: 10797063Abstract: A single-poly non-volatile memory unit includes: a semiconductor substrate having a first conductivity type; first, second and third OD regions disposed on the semiconductor substrate and separated from each other by an isolation region, wherein the first OD region and the second OD region are formed in a first ion well, and the first ion well has a second conductivity type; a first memory cell disposed on the first OD region, a second memory cell disposed on the second OD region. The first memory cell and the second memory cell exhibit an asymmetric memory cell layout structure with respect to an axis. An erase gate is disposed in the third OD region.Type: GrantFiled: December 25, 2018Date of Patent: October 6, 2020Assignee: eMemory Technology Inc.Inventors: Hsueh-Wei Chen, Wei-Ren Chen, Wein-Town Sun, Jui-Ming Kuo
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Publication number: 20200294593Abstract: An erasable programmable non-volatile memory includes a memory array and a sensing circuit. The memory array includes a general memory cell and a reference memory cell, which are connected with a word line. The sensing circuit includes a current comparator. The read current in the program state of the general memory cell is higher than the read current in the program state of the reference memory cell. The erase efficiency of the general memory cell is higher than the erase efficiency of the reference memory cell. When a read action is performed, the general memory cell generates a read current to the current comparator, and the reference memory cell generates a reference current to the current comparator. According to the reference current and the read current, the current comparator generates an output data signal to indicate a storage state of the general memory cell.Type: ApplicationFiled: February 27, 2020Publication date: September 17, 2020Inventors: Wein-Town SUN, Hsueh-Wei CHEN, Chun-Hsiao LI, Wei-Ren CHEN, Hong-Yi LIAO
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Publication number: 20190214401Abstract: A single-poly non-volatile memory unit includes: a semiconductor substrate having a first conductivity type; first, second and third OD regions disposed on the semiconductor substrate and separated from each other by an isolation region, wherein the first OD region and the second OD region are formed in a first ion well, and the first ion well has a second conductivity type; a first memory cell disposed on the first OD region, a second memory cell disposed on the second OD region. The first memory cell and the second memory cell exhibit an asymmetric memory cell layout structure with respect to an axis. An erase gate is disposed in the third OD region.Type: ApplicationFiled: December 25, 2018Publication date: July 11, 2019Inventors: Hsueh-Wei Chen, Wei-Ren Chen, Wein-Town Sun, Jui-Ming Kuo
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Patent number: 10115682Abstract: An erasable programmable non-volatile memory includes a first transistor, a second transistor, an erase gate region and a metal layer. The first transistor includes a select gate, a first doped region and a second doped region. The select gate is connected with a word line. The first doped region is connected with a source line. The second transistor includes the second doped region, a third doped region and a floating gate. The third doped region is connected with a bit line. The erase gate region is connected with an erase line. The floating gate is extended over the erase gate region and located near the erase gate region. The metal layer is disposed over the floating gate and connected with the bit line.Type: GrantFiled: April 7, 2017Date of Patent: October 30, 2018Assignee: EMEMORY TECHNOLOGY INC.Inventors: Chun-Hsiao Li, Wei-Ren Chen, Hsueh-Wei Chen
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Patent number: 9812212Abstract: A memory cell includes a program select transistor, a program element, a read select transistor, a read element, and an erase element. The program select transistor is coupled to a program source line, a program select line, and a program control line. The program element is coupled to the second terminal of the program select transistor, a program bit line, and the program control line. The read select transistor is coupled to a read source line, a read select line, and a bias control line. The read element is coupled to the second terminal of the read select transistor, a read bit line, and the bias control line. The erase element is coupled to an erase control line. A floating gate is coupled to the erase element, the program element and the read element.Type: GrantFiled: January 18, 2017Date of Patent: November 7, 2017Assignee: eMemory Technology Inc.Inventors: Hsueh-Wei Chen, Wei-Ren Chen, Wein-Town Sun
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Patent number: 9805806Abstract: A non-volatile memory cell includes a substrate, a select gate, a floating gate, and an assistant control gate. The substrate includes a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region. The select gate is formed above the first diffusion region and the second diffusion region in a polysilicon layer. The floating gate is formed above the second diffusion region, the third diffusion region and the fourth diffusion region in the polysilicon layer. The assistant control gate is formed above the floating gate in a metal layer, wherein an area of the assistant control gate overlaps with at least half an area of the floating gate.Type: GrantFiled: September 25, 2016Date of Patent: October 31, 2017Assignee: eMemory Technology Inc.Inventors: Hsueh-Wei Chen, Wei-Ren Chen, Wein-Town Sun
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Patent number: D1016792Type: GrantFiled: July 27, 2021Date of Patent: March 5, 2024Assignee: Acer IncorporatedInventors: Hsueh-Wei Chung, Pao-Ching Huang, Kai-Teng Cheng, Hung-Chi Chen