Abstract: A memory cell includes a program select transistor, a program element, a read select transistor, a read element, and an erase element. The program select transistor is coupled to a program source line, a program select line, and a program control line. The program element is coupled to the second terminal of the program select transistor, a program bit line, and the program control line. The read select transistor is coupled to a read source line, a read select line, and a bias control line. The read element is coupled to the second terminal of the read select transistor, a read bit line, and the bias control line. The erase element is coupled to an erase control line. A floating gate is coupled to the erase element, the program element and the read element.

Abstract: A non-volatile memory cell includes a substrate, a select gate, a floating gate, and an assistant control gate. The substrate includes a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region. The select gate is formed above the first diffusion region and the second diffusion region in a polysilicon layer. The floating gate is formed above the second diffusion region, the third diffusion region and the fourth diffusion region in the polysilicon layer. The assistant control gate is formed above the floating gate in a metal layer, wherein an area of the assistant control gate overlaps with at least half an area of the floating gate.

Abstract: An erasable programmable non-volatile memory includes a first transistor, a second transistor, an erase gate region and a metal layer. The first transistor includes a select gate, a first doped region and a second doped region. The select gate is connected with a word line. The first doped region is connected with a source line. The second transistor includes the second doped region, a third doped region and a floating gate. The third doped region is connected with a bit line. The erase gate region is connected with an erase line. The floating gate is extended over the erase gate region and located near the erase gate region. The metal layer is disposed over the floating gate and connected with the bit line.

Abstract: A memory cell includes a program select transistor, a program element, a read select transistor, a read element, and an erase element. The program select transistor is coupled to a program source line, a program select line, and a program control line. The program element is coupled to the second terminal of the program select transistor, a program bit line, and the program control line. The read select transistor is coupled to a read source line, a read select line, and a bias control line. The read element is coupled to the second terminal of the read select transistor, a read bit line, and the bias control line. The erase element is coupled to an erase control line. A floating gate is coupled to the erase element, the program element and the read element.

Abstract: A non-volatile memory cell includes a substrate, a select gate, a floating gate, and an assistant control gate. The substrate includes a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region. The select gate is formed above the first diffusion region and the second diffusion region in a polysilicon layer. The floating gate is formed above the second diffusion region, the third diffusion region and the fourth diffusion region in the polysilicon layer. The assistant control gate is formed above the floating gate in a metal layer, wherein an area of the assistant control gate overlaps with at least half an area of the floating gate.