Patents by Inventor Hsun Chang
Hsun Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230000349Abstract: A fundus camera includes an objective lens, an illumination device, an imaging lens group and an image sensor. The illumination device has a light emitting position and includes a plurality of light emitting modules and a driving element. Each light emitting module generates a corresponding illumination light, and the optical characteristics of the illumination lights are different from each other. The driving element drives one of the light emitting modules to the light emitting position of the illumination device to output an illumination light with required optical characteristics and irradiate it to a fundus through the objective lens. The imaging light reflected by the fundus passes through the objective lens and the imaging lens group to form an image on the image sensor so as to generate a fundus image. The abovementioned fundus camera has a compact structure and can switch the illumination light sources in a short time to obtain fundus images with different optical characteristics.Type: ApplicationFiled: June 30, 2022Publication date: January 5, 2023Inventors: Chu-Ming CHENG, Wei-hsun CHANG, Chun Yao WANG, Shao Hung HUANG, Chien Kuan CHEN
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Patent number: 11517995Abstract: The present disclosure provides a wet chemical heating system, including a first conduit for transporting wet chemical, a dispensing head connected to the first conduit, and a radiative heating element configured to heat the wet chemical in the first conduit and positioned at an upper stream of the dispensing head.Type: GrantFiled: June 21, 2019Date of Patent: December 6, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ji James Cui, Chia-Hsun Chang, Chih Hung Chen, Liang-Guang Chen, Tzu Kai Lin, Chyi Shyuan Chern, Keith Kuang-Kuo Koai
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Patent number: 11508585Abstract: A method for CMP includes following operations. A dielectric structure is received. The dielectric structure includes a metal layer stack formed therein. The metal layer stack includes at least a first metal layer and a second metal layer, and the first metal layer and the second metal layer are exposed through a surface of the dielectric structure. A first composition is provided to remove a portion of the first metal layer from the surface of the dielectric structure. A second composition is provided to form a protecting layer over the second metal layer. The protecting layer is removed from the second metal layer. A CMP operation is performed to remove a portion of the second metal layer. In some embodiments, the protecting layer protects the second metal layer during the removal of the portion of the first metal layer.Type: GrantFiled: June 15, 2020Date of Patent: November 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ji Cui, Fu-Ming Huang, Ting-Kui Chang, Tang-Kuei Chang, Chun-Chieh Lin, Wei-Wei Liang, Liang-Guang Chen, Kei-Wei Chen, Hung Yen, Ting-Hsun Chang, Chi-Hsiang Shen, Li-Chieh Wu, Chi-Jen Liu
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Patent number: 11502341Abstract: Provided is a battery charging system comprising (a) at least one charging circuit to charge at least one rechargeable battery cell; (b) a heat source to provide heat that is transported through a heat spreader element, implemented fully or partially inside said at least one battery cell, to heat up the battery cell to a desired temperature Tc before or during battery charging; and (c) cooling means in thermal contact with the heat spreader element configured to enable transporting internal heat of the battery cell through the heat spreader element to the cooling means when the battery cell is discharged. Charging the battery at Tc enables completion of the battery in less than 15 minutes, typically less than 10 minutes, and more typically less than 5 minutes without adversely impacting the battery structure and performance.Type: GrantFiled: July 24, 2019Date of Patent: November 15, 2022Assignee: Global Graphene Group, Inc.Inventors: Yu-Sheng Su, Hao-Hsun Chang, Yu-Ming Chen, Bor Z. Jang
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Publication number: 20220346203Abstract: An LED power transmission line with load identification function is coupled to an LED power control apparatus having a plurality of power output ports and an LED load. The LED power transmission line includes a power transmission circuit, a signal transmission circuit, and a memory apparatus. The power transmission circuit transmits a power outputted from the power output port to the LED load. The signal transmission circuit is coupled to a control module of the LED power apparatus through the power output port. The memory apparatus stores an LED specification information related to an electrical specification of the LED load. The LED specification information is provided to the control module through the signal transmission circuit so that the control module limits an output current outputted from the power output port according to the LED specification information.Type: ApplicationFiled: July 8, 2021Publication date: October 27, 2022Inventors: Jui-Lung CHIU, Chia-Cheng WENG, Cheng-Hsun CHANG
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Publication number: 20220344489Abstract: A semiconductor structure includes a high-k metal gate structure (HKMG) disposed over a channel region of a semiconductor layer formed over a substrate, where the HKMG includes an interfacial layer disposed over the semiconductor layer, a high-k dielectric layer disposed over the interfacial layer, and a gate electrode disposed over the high-k dielectric layer, where a length of the high-k dielectric layer is greater than a length of the gate electrode and where outer edges of the interfacial layer, the high-k dielectric layer, and the gate electrode form a step profile. The semiconductor structure further includes gate spacers having sidewall portions contacting sidewalls of the gate electrode and bottom portions contacting top portions of the high-k dielectric layer and the interfacial layer, and source/drain features disposed in the semiconductor layer adjacent to the HKMG.Type: ApplicationFiled: July 6, 2022Publication date: October 27, 2022Inventors: Jen-Hsiang Lu, Tsung-Han Tsai, Shih-Hsun Chang
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Publication number: 20220316111Abstract: A woven brushed elastic fabric includes a fabric blank and a plurality of yarn segments. The fabric blank is formed by interweaving a plurality of first yarns and composite yarns. Each composite yarn is composed of a second yarn and an elastic yarn. The second yarn is wound around the elastic yarn. The fabric blank has a first side, and a second side opposite to the first side and formed with a plurality of yarn loops. The yarn loops are formed by the interweaving of the first yarns and the composite yarns in a skip manner along a first direction or a second direction transverse to the first direction. The yarn segments are formed on the second side of the fabric blank by breaking at least some of the yarn loops.Type: ApplicationFiled: June 17, 2022Publication date: October 6, 2022Inventors: Kuo-Chin CHEN, Sung-Yun HUANG, Chia-Cheng CHOU, Chih-Wei CHEN, Li-Hsun CHANG
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Patent number: 11444339Abstract: Provided is a rechargeable battery comprising an anode, a cathode, an electrolyte disposed between the anode and the cathode, a protective housing that at least partially encloses the anode, the cathode and the electrolyte, a heat-spreader element disposed at least partially inside the protective housing and configured to receive heat from an external heat source at a desired heating temperature Th to heat up the battery to a desired temperature Tc for battery charging. Preferably, the heat-spreader element does not receive an electrical current from an external circuit (e.g. battery charger) to generate heat for resistance heating of the battery. Charging the battery at Tc enables completion of the battery in less than 15 minutes, typically less than 10 minutes, and more typically less than 5 minutes without adversely impacting the battery structure and performance.Type: GrantFiled: July 23, 2019Date of Patent: September 13, 2022Assignee: Global Graphene Group, Inc.Inventors: Yu-Sheng Su, Yu-Ming Chen, Hao-Hsun Chang, Bor Z. Jang
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Publication number: 20220285224Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The semiconductor device structure includes a spacer over a side of the gate stack. The semiconductor device structure includes a dielectric layer over the substrate. The dielectric layer has a first recess, the dielectric layer has an upper portion and a first lower portion, the upper portion is over the first recess, the first recess is between the first lower portion and the spacer, and the upper portion has a convex curved sidewall.Type: ApplicationFiled: May 24, 2022Publication date: September 8, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Heng TSAI, Chun-Sheng LIANG, Pei-Lin WU, Yi-Ren CHEN, Shih-Hsun CHANG
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Publication number: 20220250124Abstract: An apparatus includes a casing configured to be detachably mounted on a workpiece. The casing includes a first opening configured to expose a portion of the workpiece; a first support member coupled to the casing and constructed to move along a first axis through the casing and rotate around the first axis; a second support member coupled to the first support member and constructed to move along a second axis perpendicular to the first axis; an arm pivotally coupled to the second support member and constructed to rotate around a third axis perpendicular to the first axis and the second axis; and a cleaning head attached to the arm and constructed to rotate around a longitudinal axis of the arm. The casing includes a first plate and a second plate opposite to the first plate, wherein the cleaning head is configured to extend outside the casing through the first opening.Type: ApplicationFiled: April 26, 2022Publication date: August 11, 2022Inventors: SHIH-KUO LIU, CHIA-HSUN CHANG, KEITH KUANG-KUO KOAI, WAI HONG CHEAH, MING-CHUAN HUNG
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Patent number: 11404555Abstract: A semiconductor structure includes a high-k metal gate structure (HKMG) disposed over a channel region of a semiconductor layer formed over a substrate, where the HKMG includes an interfacial layer disposed over the semiconductor layer, a high-k dielectric layer disposed over the interfacial layer, and a gate electrode disposed over the high-k dielectric layer, where a length of the high-k dielectric layer is greater than a length of the gate electrode and where outer edges of the interfacial layer, the high-k dielectric layer, and the gate electrode form a step profile. The semiconductor structure further includes gate spacers having sidewall portions contacting sidewalls of the gate electrode and bottom portions contacting top portions of the high-k dielectric layer and the interfacial layer, and source/drain features disposed in the semiconductor layer adjacent to the HKMG.Type: GrantFiled: May 4, 2020Date of Patent: August 2, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jen-Hsiang Lu, Tsung-Han Tsai, Shih-Hsun Chang
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Patent number: 11404418Abstract: A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins.Type: GrantFiled: September 28, 2020Date of Patent: August 2, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Chun Liao, Chun-Sheng Liang, Shu-Hui Wang, Shih-Hsun Chang, Yi-Jen Chen
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Patent number: 11390528Abstract: Provided is an anode for a lithium battery or sodium battery, the anode comprising multiple porous graphene balls and multiple particles or coating of a lithium-attracting metal or sodium-attracting metal at a graphene ball-to-metal volume ratio from 5/95 to 95/5, wherein the porous graphene ball comprises a plurality of graphene sheets forming into the ball having a diameter from 100 nm to 20 ?m and a pore or multiple pores having a pore volume fraction from 10% to 99.9% based on the total graphene ball volume, and wherein the particles or coating of lithium-attracting metal or sodium-attracting metal, having a diameter or thickness from 1 nm to 20 ?m, are selected from Au, Ag, Mg, Zn, Ti, K, Al, Fe, Mn, Co, Ni, Sn, V, Cr, an alloy thereof, or a combination thereof.Type: GrantFiled: November 26, 2019Date of Patent: July 19, 2022Assignee: Global Graphene Group, Inc.Inventors: Aruna Zhamu, Hao-Hsun Chang, Bor Z. Jang
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Patent number: 11348841Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate, wherein the gate stack has a first portion and a second portion under the first portion, and the first portion is wider than the second portion. The semiconductor device structure includes a first spacer and a second spacer over opposite sides of the gate stack. The first spacer has a first upper portion and a first lower portion, the second spacer has a second upper portion and a second lower portion. The first spacer has a first recess, the first upper portion is between the first recess and the gate stack, the first lower portion is under the first recess, and the first recess has a first inner wall facing away from the gate stack.Type: GrantFiled: August 28, 2020Date of Patent: May 31, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Heng Tsai, Chun-Sheng Liang, Pei-Lin Wu, Yi-Ren Chen, Shih-Hsun Chang
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Publication number: 20220157781Abstract: An electronic device includes a circuit board, a package on package structure, a heat-conducting cover, and a heat-conducting fluid. The circuit board has a first surface and a second surface opposite to each other. The package on package structure is disposed on the first surface. The package on package structure has at least one heat generating element. The heat-conducting cover is disposed on the second surface and is in thermal contact with the circuit board. The heat-conducting cover and the second surface form an enclosed space. The heat-conducting fluid is filled in the enclosed space.Type: ApplicationFiled: July 28, 2021Publication date: May 19, 2022Applicant: HTC CorporationInventors: Li-Hsun Chang, Kuan-Ying Ou, Wei-Jen Chen
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Patent number: 11318506Abstract: An apparatus includes a first support member coupled to a casing and constructed to move along a first axis through the casing and rotate around the first axis, a second support member coupled to the first support member and constructed to move along a second axis perpendicular to the first axis, and an arm pivotally coupled to the second support member and constructed to rotate around a third axis perpendicular to the first axis and the second axis. The apparatus also includes a cleaning head attached to the arm and constructed to rotate around a longitudinal axis of the arm.Type: GrantFiled: June 14, 2019Date of Patent: May 3, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Shih-Kuo Liu, Chia-Hsun Chang, Keith Kuang-Kuo Koai, Wai Hong Cheah, Ming-Chuan Hung
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Patent number: 11295990Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.Type: GrantFiled: January 6, 2020Date of Patent: April 5, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ju-Li Huang, Hsin-Che Chiang, Ju-Yuan Tzeng, Wei-Ze Xu, Yueh-Yi Chen, Shu-Hui Wang, Shih-Hsun Chang
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Publication number: 20220102147Abstract: A method includes removing a dummy gate to form a gate trench. A gate dielectric layer is deposited over a bottom and sidewalls of the gate trench. A first work function metal layer is deposited over the gate dielectric layer. A dummy layer is deposited over the first work function metal layer. An impurity is introduced into the dummy layer and the first work function metal layer after the dummy layer is deposited. The dummy layer is removed after the impurity is introduced into the dummy layer and the first work function metal layer. The gate trench is filled with a conductive material after the dummy layer is removed.Type: ApplicationFiled: December 13, 2021Publication date: March 31, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Yu CHEN, Yu-Chi LU, Chih-Pin TSAO, Shih-Hsun CHANG
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Publication number: 20220099910Abstract: A head mounted display including a first optical system, a second optical system, a first display, a second display, a first driver and a first adjusting system is provided. The first display is assembled to an object side of the first optical system. The second display is assembled to an object side of the second optical system. The first adjusting system is connected to the first driver, the first optical system, the first display and the second display. The first driver drives the first adjusting system to adjust a distance between the first display and the second display in a first mode. The first driver drives the first adjusting system to adjust a distance between the first display and the first optical system in a second mode.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Applicant: HTC CorporationInventors: Li-Hsun Chang, Kuan-Ying Ou
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Publication number: 20220069313Abstract: Provided is an anode electrode (e.g. a layer or roll of a laminated structure) for a lithium battery or sodium battery, the anode electrode comprising: (a) an anode current collector having two primary surfaces; (b) multiple particles or coating of a lithium-attracting metal or sodium-attracting metal deposited on at least one of the two primary surfaces, wherein the lithium-attracting metal or sodium-attracting metal, having a diameter or thickness from 1 nm to 10 ?m, is selected from Au, Ag, Mg, Zn, Ti, K, Al, Fe, Mn, Co, Ni, Sn, V, Cr, an alloy thereof, or a combination thereof; and (c) a layer of graphene that covers and protects the multiple particles or coating of the metal. Also provided is a process for producing such an anode electrode and a battery cell.Type: ApplicationFiled: August 28, 2020Publication date: March 3, 2022Inventors: Hui He, Aruna Zhamu, Hao-Hsun Chang, Bor Z. Jang