Patents by Inventor Hsun-Chih Tsao
Hsun-Chih Tsao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9335827Abstract: A gesture input system with a two-dimension (2D) image sensor and a processing module is provided. The 2D image sensor obtains a plurality of images of a user. The processing module determines positions of an object and a face of the user in a first image of the plurality of images, and determines an operation area for the user according to the positions of the object and the face. Also, the processing module generates a control command according to the subsequent images to the first image of the user within the operation area.Type: GrantFiled: May 22, 2013Date of Patent: May 10, 2016Assignee: Wistron Corp.Inventors: Chih-Hao Huang, Hsun-Chih Tsao, Chih-Pin Liao, Pin-Hong Liou
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Patent number: 9268408Abstract: An operating area determination method and system are provided. In the operating area determination method, a plurality of depth maps of a target scene is generated at several time points. At least two specific depth maps among the depth maps are selected and compared to identify a moving object in the target scene, and a position of the moving object in the target scene is defined as a reference point. A standard point in the target scene is obtained according to the reference point and a specific depth corresponding to the reference point. An effective operating area in the target scene is determined according to the reference point and the standard point for controlling an electronic apparatus.Type: GrantFiled: February 20, 2013Date of Patent: February 23, 2016Assignee: Wistron CorporationInventors: Chia-Te Chou, Shou-Te Wei, Hsun-Chih Tsao, Chih-Hsuan Lee
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Patent number: 9003435Abstract: A method of recommending media content for a media playing system includes identifying a user in a viewing area; determining whether personal information of the user is stored in a database; and generating information related to a first media content recommendation according to the personal information when the personal information of the user is stored in the database.Type: GrantFiled: October 7, 2013Date of Patent: April 7, 2015Assignee: Wistron CorporationInventors: Hsi-Chun Hsiao, Shou-Te Wei, Hsun-Chih Tsao
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Patent number: 8937589Abstract: A gesture control method includes steps of capturing at least one image; detecting whether there is a face in the at least one image; if there is a face in the at least one image, detecting whether there is a hand in the at least one image; if there is a hand in the at least one image, identifying a gesture performed by the hand and identifying a relative distance or a relative moving speed between the hand and the face; and executing a predetermined function in a display screen according to the gesture and the relative distance or according to the gesture and the relative moving speed.Type: GrantFiled: September 5, 2012Date of Patent: January 20, 2015Assignee: Wistron CorporationInventors: Shou-Te Wei, Chia-Te Chou, Hsun-Chih Tsao, Chih-Pin Liao
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Publication number: 20140215504Abstract: A method of recommending media content for a media playing system includes identifying a user in a viewing area; determining whether personal information of the user is stored in a database; and generating information related to a first media content recommendation according to the personal information when the personal information of the user is stored in the database.Type: ApplicationFiled: October 7, 2013Publication date: July 31, 2014Applicant: Wistron CorporationInventors: Hsi-Chun Hsiao, Shou-Te Wei, Hsun-Chih Tsao
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Publication number: 20140078040Abstract: A dual-mode remote control method, adapted to an electronic apparatus having an image sensor, is provided. In the method, the image sensor is used to successively capture a plurality of images. Then, infrared ray (IR) detection and/or gesture detection is determined according to at least one characteristic of the images and performed on the images, so as to obtain an action of at least one target in the images. Finally, a control command corresponding to the action is executed.Type: ApplicationFiled: December 28, 2012Publication date: March 20, 2014Applicant: Wistron CorporationInventors: Sheng-Hsien Hsieh, Shou-Te Wei, Sheng-Hua Chou, Pin-Hong Liou, Che-You Kuo, Chih-Hao Huang, Hsun-Chih Tsao
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Publication number: 20140022172Abstract: A gesture input system with a two-dimension (2D) image sensor and a processing module is provided. The 2D image sensor obtains a plurality of images of a user. The processing module determines positions of an object and a face of the user in a first image of the plurality of images, and determines an operation area for the user according to the positions of the object and the face. Also, the processing module generates a control command according to the subsequent images to the first image of the user within the operation area.Type: ApplicationFiled: May 22, 2013Publication date: January 23, 2014Applicant: Wistron Corp.Inventors: Chih-Hao Huang, Hsun-Chih Tsao, Chih-Pin Liao, Pin-Hong Liou
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Publication number: 20130321404Abstract: An operating area determination method and system are provided. In the operating area determination method, a plurality of depth maps of a target scene is generated at several time points. At least two specific depth maps among the depth maps are selected and compared to identify a moving object in the target scene, and a position of the moving object in the target scene is defined as a reference point. A standard point in the target scene is obtained according to the reference point and a specific depth corresponding to the reference point. An effective operating area in the target scene is determined according to the reference point and the standard point for controlling an electronic apparatus.Type: ApplicationFiled: February 20, 2013Publication date: December 5, 2013Applicant: WISTRON CORPORATIONInventors: Chia-Te Chou, Shou-Te Wei, Hsun-Chih Tsao, Chih-Hsuan Lee
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Publication number: 20130278493Abstract: A gesture control method includes steps of capturing at least one image; detecting whether there is a face in the at least one image; if there is a face in the at least one image, detecting whether there is a hand in the at least one image; if there is a hand in the at least one image, identifying a gesture performed by the hand and identifying a relative distance or a relative moving speed between the hand and the face; and executing a predetermined function in a display screen according to the gesture and the relative distance or according to the gesture and the relative moving speed.Type: ApplicationFiled: September 5, 2012Publication date: October 24, 2013Inventors: Shou-Te Wei, Chia-Te Chou, Hsun-Chih Tsao, Chih-Pin Liao
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Publication number: 20130141394Abstract: An electronic system is provided, including a writing device, first and second image capturing units and a control module. The writing device has a pen point to write on a writing board, and has a first light-emitting unit to emit a first detection light. The first and second image capturing units are respectively disposed on a first corner and a second corner of the writing board to receive the first detection light in a writing mode, in order to respectively generate first and second image signals. The control module obtains the coordinates of the writing device on the writing board according to the first and second image signals, such that, when the writing device writes on the writing board, the control module determines to operate in the writing mode, and simultaneously records a writing track of the writing device.Type: ApplicationFiled: September 10, 2012Publication date: June 6, 2013Applicant: WISTRON CORP.Inventors: Chia-Te Chou, Shou-Te Wei, Hsun-Chih Tsao
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Patent number: 7663185Abstract: A fin-FET device and a method for fabrication thereof both employ a bulk semiconductor substrate. A fin and an adjoining trough are formed within the bulk semiconductor substrate. The trough is partially backfilled with a deposited dielectric layer to form an exposed fin region and an unexposed fin region. A gate dielectric layer is formed upon the exposed fin region and a gate electrode is formed upon the gate dielectric layer. By employing a bulk semiconductor substrate the fin-FET device is fabricated cost effectively.Type: GrantFiled: May 27, 2006Date of Patent: February 16, 2010Assignee: Taiwan Semiconductor Manufacturing Co, LtdInventors: Kuang-Hsin Chen, Hsun-Chih Tsao, Jhi-Cherng Lu, Chuan-Ping Hou, Peng-Fu Hsu, Hung-Wei Chen, Di-Hong Lee
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Patent number: 7638376Abstract: A method for forming a substrate contact on a silicon-on-insulator (SOI) wafer is provided that can be integrated with a process for fabricating SOI devices without additional processing after wafer dicing. The method is applicable in many of the more advanced packaging technologies, e.g., such as flip chip and die stacking, directly creating a contact to silicon substrate via the front of the diced SOI wafer.Type: GrantFiled: January 12, 2007Date of Patent: December 29, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Kuo Wen, Chien-Chao Huang, Hao-Yu Chen, Fu-Liang Yang, Hsun-Chih Tsao
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Patent number: 7633127Abstract: A method in which a gate and raised source/drain (S/D) regions are fully silicided in separate steps to avoid degrading the resistance or junction leakage is described. A gate dielectric layer, gate, and spacers are formed over a semiconductor layer that is preferably Si, SiGe, or SiGeC on a buried insulator. Raised S/D regions are formed by selective epitaxy between spacers and isolation regions. The gate is protected with a mask while the raised S/D regions are covered with a first metal layer. A first anneal affords fully silicided S/D regions. A dielectric stack is deposited on the substrate and planarized to be coplanar with the top of the spacers. The mask is removed and a second metal layer is deposited. A second anneal yields a fully silicided gate electrode. The invention is also an SOI transistor with silicided raised S/D regions and a fully silicided and optionally recessed gate.Type: GrantFiled: May 4, 2006Date of Patent: December 15, 2009Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Cheng-Kuo Wen, Yee-Chia Yeo, Hsun-Chih Tsao
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Patent number: 7538351Abstract: A semiconductor device and method for forming the same including improved electrostatic discharge protection for advanced semiconductor devices, the semiconductor device including providing semiconductor substrate having a pre-selected surface orientation and crystal direction; an insulator layer overlying the semiconductor substrate; a first semiconductor active region overlying the insulator layer having a first surface orientation selected from the group consisting of <100> and <110>; a second semiconductor active region extending through a thickness portion of the insulator layer having a second surface orientation selected from the group consisting of <110> and <100> different from the first surface orientation; wherein MOS devices including a first MOS device of a first conduction type is disposed on the first semiconductor active region and a second MOS device of a second conduction type is disposed on the second semiconductor active region.Type: GrantFiled: March 23, 2005Date of Patent: May 26, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Wei Chen, Hsun-Chih Tsao, Kuang-Hsin Chen, Di-Hong Lee
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Publication number: 20080171419Abstract: A method for forming a substrate contact on a silicon-on-insulator (SOI) wafer is provided that can be integrated with a process for fabricating SOI devices without additional processing after wafer dicing. The method is applicable in many of the more advanced packaging technologies, e.g., such as flip chip and die stacking, directly creating a contact to silicon substrate via the front of the diced SOI wafer.Type: ApplicationFiled: January 12, 2007Publication date: July 17, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Kuo Wen, Chien-Chao Huang, Hao-Yu Chen, Fu-Liang Yang, Hsun-Chih Tsao
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Patent number: 7332777Abstract: In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.Type: GrantFiled: September 7, 2005Date of Patent: February 19, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuang-Hsin Chen, Hsun-Chih Tsao, Hung-Wei Chen, Di-Hong Lee, Chuan-Ping Hou, Jhi-Cherng Lu
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Publication number: 20070272954Abstract: A fin-FET device and a method for fabrication thereof both employ a bulk semiconductor substrate. A fin and an adjoining trough are formed within the bulk semiconductor substrate. The trough is partially backfilled with a deposited dielectric layer to form an exposed fin region and an unexposed fin region. A gate dielectric layer is formed upon the exposed fin region and a gate electrode is formed upon the gate dielectric layer. By employing a bulk semiconductor substrate the fin-FET device is fabricated cost effectively.Type: ApplicationFiled: May 27, 2006Publication date: November 29, 2007Inventors: Kuang-Hsin Chen, Hsun-Chih Tsao, Jhi-Cherng Lu, Chuan-Ping Hou, Peng-Fu Hsu, Hung-Wei Chen, Di-Hong Lee
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Patent number: 7205601Abstract: A FinFET split gate EEPROM structure includes a semiconductor substrate and an elongated semiconductor fin extending above the substrate. A control gate straddles the fin, the fin's sides and a first drain-proximate portion of a channel between a source and drain in the fin. The control gate includes a tunnel layer and a floating electrode over which are a first insulative stratum and a first conductive stratum. A select gate straddles the fin and its sides and a second, source-promixate portion of the channel. The select gate includes a second insulative stratum and a second conductive stratum. The insulative strata are portions of a continuous insulative layer covering the substrate and the fin. The conductive strata are electrically continuous portions of a continuous conductive layer formed on the insulative layer.Type: GrantFiled: June 9, 2005Date of Patent: April 17, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Di-Hong Lee, Hsun-Chih Tsao, Kuang-Hsin Chen, Hung-Wei Chen
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Patent number: 7183150Abstract: In accordance with the objectives of the invention a new method is provided for the creation of a layer of a Resistance Protective Oxide (RPO) layer. A layer of ONO is deposited that is to function as the layer of RPO. The deposited layer of ONO is patterned and wet etched, removing the upper or first layer of silicon dioxide. The patterned and etch upper of first layer of silicon dioxide is used as a hardmask to remove the central layer of silicon nitride applying a wet etch. A wet etch is then applied to remove the remaining lower of second layer of silicon dioxide, completing the patterning of the layer of RPO.Type: GrantFiled: September 21, 2004Date of Patent: February 27, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Chang Hsieh, Hsun-Chih Tsao, Hung-Chih Tsai, Pin-Shyne Chin
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Publication number: 20060278915Abstract: A FinFET split gate EEPROM structure includes a semiconductor substrate and an elongated semiconductor fin extending above the substrate. A control gate straddles the fin, the fin's sides and a first drain-proximate portion of a channel between a source and drain in the fin. The control gate includes a tunnel layer and a floating electrode over which are a first insulative stratum and a first conductive stratum. A select gate straddles the fin and its sides and a second, source-promixate portion of the channel. The select gate includes a second insulative stratum and a second conductive stratum. The insulative strata are portions of a continuous insulative layer covering the substrate and the fin. The conductive strata are electrically continuous portions of a continuous conductive layer formed on the insulative layer.Type: ApplicationFiled: June 9, 2005Publication date: December 14, 2006Inventors: Di-Hong Lee, Hsun-Chih Tsao, Kuang-Hsin Chen, Hung-Wei Chen