Patents by Inventor Hsun-Chih Tsao
Hsun-Chih Tsao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20060214226Abstract: A semiconductor device and method for forming the same including improved electrostatic discharge protection for advanced semiconductor devices, the semiconductor device including providing semiconductor substrate having a pre-selected surface orientation and crystal direction; an insulator layer overlying the semiconductor substrate; a first semiconductor active region overlying the insulator layer having a first surface orientation selected from the group consisting of <100> and <110>; a second semiconductor active region extending through a thickness portion of the insulator layer having a second surface orientation selected from the group consisting of <110> and <100> different from the first surface orientation; wherein MOS devices including a first MOS device of a first conduction type is disposed on the first semiconductor active region and a second MOS device of a second conduction type is disposed on the second semiconductor active region.Type: ApplicationFiled: March 23, 2005Publication date: September 28, 2006Inventors: Hung-Wei Chen, Hsun-Chih Tsao, Kuang-Hsin Chen, Di-Hong Lee
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Publication number: 20060194399Abstract: A method in which a gate and raised source/drain (S/D) regions are fully silicided in separate steps to avoid degrading the resistance or junction leakage is described. A gate dielectric layer, gate, and spacers are formed over a semiconductor layer that is preferably Si, SiGe, or SiGeC on a buried insulator. Raised S/D regions are formed by selective epitaxy between spacers and isolation regions. The gate is protected with a mask while the raised S/D regions are covered with a first metal layer. A first anneal affords fully silicided S/D regions. A dielectric stack is deposited on the substrate and planarized to be coplanar with the top of the spacers. The mask is removed and a second metal layer is deposited. A second anneal yields a fully silicided gate electrode. The invention is also an SOI transistor with silicided raised S/D regions and a fully silicided and optionally recessed gate.Type: ApplicationFiled: May 4, 2006Publication date: August 31, 2006Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Kuo Wen, Yee-Chia Yeo, Hsun-Chih Tsao
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Patent number: 7067379Abstract: A method in which a gate and raised source/drain (S/D) regions are fully silicided in separate steps to avoid degrading the resistance or junction leakage is described. A gate dielectric layer, gate, and spacers are formed over a semiconductor layer that is preferably Si, SiGe, or SiGeC on a buried insulator. Raised S/D regions are formed by selective epitaxy between spacers and isolation regions. The gate is protected with a mask while the raised S/D regions are covered with a first metal layer. A first anneal affords fully silicided S/D regions. A dielectric stack is deposited on the substrate and planarized to be coplanar with the top of the spacers. The mask is removed and a second metal layer is deposited. A second anneal yields a fully silicided gate electrode. The invention is also an SOI transistor with silicided raised S/D regions and a fully silicided and optionally recessed gate.Type: GrantFiled: January 8, 2004Date of Patent: June 27, 2006Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Kuo Wen, Yee-Chia Yeo, Hsun-Chih Tsao
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Patent number: 7053453Abstract: A substrate contact and semiconductor chip, and methods of forming the same. The substrate contact is employable with a semiconductor chip formed from a semiconductor substrate and includes a seal ring region about a periphery of an integrated circuit region. In one embodiment, the substrate contact includes a contact trench extending through a shallow trench isolation region and an insulator overlying the semiconductor substrate and outside the integrated circuit region. The contact trench is substantially filled with a conductive material thereby allowing the semiconductor substrate to be electrically connected with a metal interconnect within the seal ring region.Type: GrantFiled: June 8, 2004Date of Patent: May 30, 2006Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsun-Chih Tsao, Chien-Chao Huang, Fu-Liang Yang
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Patent number: 7026196Abstract: A method for forming a field effect transistor includes: forming a conductive region on an isolation layer formed on a substrate, and a cap dielectric layer on the conductive region; forming a sacrificial dielectric layer over the isolation layer and the cap dielectric layer, and on sidewalls of the conductive region; removing a portion of the sacrificial dielectric layer on the cap dielectric layer; removing the cap dielectric layer; removing remaining portions of the sacrificial dielectric layer; forming a gate on the conductive region; and forming source/drain (S/D) regions within the conductive region and adjacent to the gate. A field effect transistor includes a conductive region over an isolation layer formed on a substrate, the conductive region being substantially without undercut at the region within the isolation layer beneath the conductive region; a gate on the conductive region; and S/D regions within the conductive region and adjacent to the gate.Type: GrantFiled: November 24, 2003Date of Patent: April 11, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chuan-Ping Hou, Jhi-Cherng Lu, Kuang-Hsin Chen, Hsun-Chih Tsao
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Publication number: 20060012004Abstract: In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.Type: ApplicationFiled: September 7, 2005Publication date: January 19, 2006Inventors: Kuang-Hsin Chen, Hsun-Chih Tsao, Hung-Wei Chen, Di-Hong Lee, Chuan-Ping Hou, Jhi-Cherng Lu
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Patent number: 6979867Abstract: A semiconductor-on-insulator structure includes a substrate and a buried insulator layer overlying the substrate. A plurality of semiconductor islands overlie the buried insulator layer. The semiconductor islands are isolated from one another by trenches. A plurality of recess resistant regions overlie the buried insulator layer at a lower surface of the trenches.Type: GrantFiled: December 27, 2004Date of Patent: December 27, 2005Assignee: Taiwan Semiconductor Manufacturing Ltd. Co.Inventors: Yee-Chia Yeo, Hao-Yu Chen, Hsun-Chih Tsao, Fu-Liang Yang, Chenming Hu
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Publication number: 20050236712Abstract: A substrate contact and semiconductor chip, and methods of forming the same. The substrate contact is employable with a semiconductor chip formed from a semiconductor substrate and includes a seal ring region about a periphery of an integrated circuit region. In one embodiment, the substrate contact includes a contact trench extending through a shallow trench isolation region and an insulator overlying the semiconductor substrate and outside the integrated circuit region. The contact trench is substantially filled with a conductive material thereby allowing the semiconductor substrate to be electrically connected with a metal interconnect within the seal ring region.Type: ApplicationFiled: June 8, 2004Publication date: October 27, 2005Inventors: Hsun-Chih Tsao, Chien-Chao Huang, Fu-Liang Yang
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Patent number: 6955955Abstract: In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.Type: GrantFiled: December 29, 2003Date of Patent: October 18, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuang-Hsin Chen, Hsun-Chih Tsao, Hung-Wei Chen, Di-Hong Lee, Chuan-Ping Hou, Jhi-Cherng Lu
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Publication number: 20050156238Abstract: A method in which a gate and raised source/drain (S/D) regions are fully silicided in separate steps to avoid degrading the resistance or junction leakage is described. A gate dielectric layer, gate, and spacers are formed over a semiconductor layer that is preferably Si, SiGe, or SiGeC on a buried insulator. Raised S/D regions are formed by selective epitaxy between spacers and isolation regions. The gate is protected with a mask while the raised S/D regions are covered with a first metal layer. A first anneal affords fully silicided S/D regions. A dielectric stack is deposited on the substrate and planarized to be coplanar with the top of the spacers. The mask is removed and a second metal layer is deposited. A second anneal yields a fully silicided gate electrode. The invention is also an SOI transistor with silicided raised S/D regions and a fully silicided and optionally recessed gate.Type: ApplicationFiled: January 8, 2004Publication date: July 21, 2005Inventors: Cheng-Kuo Wen, Yee-Chia Yeo, Hsun-Chih Tsao
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Publication number: 20050145937Abstract: In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.Type: ApplicationFiled: December 29, 2003Publication date: July 7, 2005Inventors: Kuang-Hsin Chen, Hsun-Chih Tsao, Hung-Wei Chen, Di-Hong Lee, Chuan-Ping Hou, Jhi-Cherng Lu
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Publication number: 20050110086Abstract: A method for forming a field effect transistor includes: forming a conductive region on an isolation layer formed on a substrate, and a cap dielectric layer on the conductive region; forming a sacrificial dielectric layer over the isolation layer and the cap dielectric layer, and on sidewalls of the conductive region; removing a portion of the sacrificial dielectric layer on the cap dielectric layer; removing the cap dielectric layer; removing remaining portions of the sacrificial dielectric layer; forming a gate on the conductive region; and forming source/drain (S/D) regions within the conductive region and adjacent to the gate. A field effect transistor includes a conductive region over an isolation layer formed on a substrate, the conductive region being substantially without undercut at the region within the isolation layer beneath the conductive region; a gate on the conductive region; and S/D regions within the conductive region and adjacent to the gate.Type: ApplicationFiled: November 24, 2003Publication date: May 26, 2005Inventors: Chuan-Ping Hou, Jhi-Cherng Lu, Kuang-Hsin Chen, Hsun-Chih Tsao
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Publication number: 20050101111Abstract: A semiconductor-on-insulator structure includes a substrate and a buried insulator layer overlying the substrate. A plurality of semiconductor islands overlie the buried insulator layer. The semiconductor islands are isolated from one another by trenches. A plurality of recess resistant regions overlie the buried insulator layer at a lower surface of the trenches.Type: ApplicationFiled: December 27, 2004Publication date: May 12, 2005Inventors: Yee-Chia Yeo, Hao-Yu Chen, Hsun-Chih Tsao, Fu-Liang Yang, Chenming Hu
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Patent number: 6864149Abstract: A semiconductor-on-insulator structure includes a substrate and a buried insulator layer overlying the substrate. A plurality of semiconductor islands overlie the buried insulator layer. The semiconductor islands are isolated from one another by trenches. A plurality of recess resistant regions overlie the buried insulator layer at a lower surface of the trenches.Type: GrantFiled: May 9, 2003Date of Patent: March 8, 2005Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yee-Chia Yeo, Hao-Yu Chen, Hsun-Chih Tsao, Fu-Liang Yang, Chenming Hu
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Publication number: 20050037623Abstract: In accordance with the objectives of the invention a new method is provided for the creation of a layer of a Resistance Protective Oxide (RPO) layer. A layer of ONO is deposited that is to function as the layer of RPO. The deposited layer of ONO is patterned and wet etched, removing the upper or first layer of silicon dioxide. The patterned and etch upper of first layer of silicon dioxide is used as a hardmask to remove the central layer of silicon nitride applying a wet etch. A wet etch is then applied to remove the remaining lower of second layer of silicon dioxide, completing the patterning of the layer of RPO.Type: ApplicationFiled: September 21, 2004Publication date: February 17, 2005Inventors: Ming-Chang Hsieh, Hsun-Chih Tsao, Hung-Chih Tsai, Pin-Shyne Chin
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Publication number: 20040222463Abstract: A semiconductor-on-insulator structure includes a substrate and a buried insulator layer overlying the substrate. A plurality of semiconductor islands overlie the buried insulator layer. The semiconductor islands are isolated from one another by trenches. A plurality of recess resistant regions overlie the buried insulator layer at a lower surface of the trenches.Type: ApplicationFiled: May 9, 2003Publication date: November 11, 2004Inventors: Yee-Chia Yeo, Hao-Yu Chen, Hsun-Chih Tsao, Fu-Liang Yang, Chenming Hu
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Patent number: 6815274Abstract: In accordance with the objectives of the invention a new method is provided for the creation of a layer of a Resistance Protective Oxide (RPO) layer. A layer of ONO is deposited that is to function as the layer of RPO. The deposited layer of ONO is patterned and wet etched, removing the upper or first layer of silicon dioxide. The patterned and etch upper of first layer of silicon dioxide is used as a hardmask to remove the central layer of silicon nitride applying a wet etch. A wet etch is then applied to remove the remaining lower of second layer of silicon dioxide, completing the patterning of the layer of RPO.Type: GrantFiled: September 13, 2002Date of Patent: November 9, 2004Assignee: Taiwan Semiconductor Manufacturing Co.Inventors: Ming-Chang Hsieh, Hsun-Chih Tsao, Hung-Chih Tsai, Pin-Shyne Chin
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Patent number: 6191018Abstract: A method for forming a polycide layer wherein the silicide layer is blanket deposited over a polysilicon layer and selectively ion implanted through a mask to form regions of a higher resistivity than the masked regions. The implanted polycide layer is then annealed by RTA and patterned to form the conductors, gate electrodes and interconnects from the low resistivity regions and resistive components of an integrated circuit from the high resistivity regions. The capability of selecting from high and low resistive regions in a single polycide layer permits the design of resistive components with smaller areas than would be permitted if the resistive components were formed of a single low resistivity layer. This extra degree of freedom permits the designer to optimize device density and device performance without compromising either. The procedure utilizes a additional masking step utilizing a block-out mask.Type: GrantFiled: January 4, 1999Date of Patent: February 20, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Wen-Jye Yue, Hsun-Chih Tsao, Tzong-Sheng Chang