Abstract: An organic-inorganic hybrid resin, a molding composition, and a photoelectric device employing the same are disclosed. The organic-inorganic hybrid resin is a reaction product of a composition, wherein the composition includes: 0.1-10 parts by weight of reactant (a), and 100 parts by weight of reactant (b). In particular, the reactant (a) is a silsesquioxane prepolymer with metal oxide clusters, and the metal oxide cluster includes Ti, Zr, Zn, or a combination thereof. The reactant (b) includes an epoxy resin.

Abstract: An organic-inorganic hybrid resin, a molding composition, and a photoelectric device employing the same are disclosed. The organic-inorganic hybrid resin is a reaction product of a composition, wherein the composition includes: 0.1-10 parts by weight of reactant (a), and 100 parts by weight of reactant (b). In particular, the reactant (a) is a silsesquioxane prepolymer with metal oxide clusters, and the metal oxide cluster includes Ti, Zr, Zn, or a combination thereof. The reactant (b) includes an epoxy resin.

Abstract: In one embodiment, an organic-inorganic metal oxide hybrid resin having the following formula: wherein each R1 is independently a substituted or non-substituted C1 to C10 alkyl group; each R2 is independently a substituted or non-substituted C1 to C10 alkyl group or benzyl group; n is a positive integer from 3 to 30; and each Y is independently (MO4/2)l[(MO)(4-a)/2M(OH)a/2]m[MO(4-b)/2M(OZ)b/2]p, wherein M is a metal; l is a positive integer from 10 to 90; m is a positive integer from 2 to 20; p is a positive integer from 4 to 15; a is a positive integer from 1 to 2; b is a positive integer from 1 to 2; and Z is an organosilane group.

Abstract: In one embodiment, an organic-inorganic metal oxide hybrid resin having the following formula: wherein each R1 is independently a substituted or non-substituted C1 to C10 alkyl group; each R2 is independently a substituted or non-substituted C1 to C10 alkyl group or benzyl group; n is a positive integer from 3 to 30; and each Y is independently (MO4/2)l[(MO)(4-a)/2M(OH)a/2]m[MO(4-b)/2M(OZ)b/2]p, wherein M is a metal; l is a positive integer from 10 to 90; m is a positive integer from 2 to 20; p is a positive integer from 4 to 15; a is a positive integer from 1 to 2; b is a positive integer from 1 to 2; and Z is an organosilane group.

Abstract: A transparent silicone epoxy composition is provided. The transparent silicone epoxy composition comprises (a) at least an epoxy modified siloxane, (b) at least a silanol-containing siloxane and (c) a catalyst. Each epoxy modified siloxane molecule comprises at least two cycloaliphatic epoxy groups and epoxy modified siloxane in the transparent silicone epoxy composition is about 10˜89 weight percentage. Silanol-containing siloxane can be cross-linked with epoxy modified siloxane. Silanol-containing siloxane comprises at least two hydroxyl groups. Silanol-containing siloxane in the transparent silicone epoxy composition is about 89˜10 weight percentage. The catalyst in the transparent silicone epoxy composition is about 0.01˜1 weight percentage.

Abstract: A transparent silicone epoxy composition is provided. The transparent silicone epoxy composition comprises (a) at least an epoxy modified siloxane, (b) at least a silanol-containing siloxane and (c) a catalyst. Each epoxy modified siloxane molecule comprises at least two cycloaliphatic epoxy groups and epoxy modified siloxane in the transparent silicone epoxy composition is about 10˜89 weight percentage. Silanol-containing siloxane can be cross-linked with epoxy modified siloxane. Silanol-containing siloxane comprises at least two hydroxyl groups. Silanol-containing siloxane in the transparent silicone epoxy composition is about 89˜10 weight percentage. The catalyst in the transparent silicone epoxy composition is about 0.01˜1 weight percentage.

Abstract: An encapsulant composition for a light-emitting diode is provided. One embodiment of the encapsulant composition comprises: (a) about 100 parts by weight of at least one liquid bi-functional epoxy resin containing about 40˜50 weight % of aromatic ring; (b) about 55˜120 parts by weight of a curing agent comprising at least one bi-functional thiol curing agent containing aromatic ring and at least one aliphatic tetra-functional thiol curing agent, wherein the curing agent contains about 10˜50 weight % of aromatic ring and about 20˜35 weight % of sulfur; and (c) about 0.05˜0.5 parts by weight of a catalyst. The encapsulant composition having a high refractive index can be used for a solid state light emitting device to enhance light extraction efficiency.

Abstract: An encapsulant composition for a light-emitting diode is provided. One embodiment of the encapsulant composition comprises: (a) about 100 parts by weight of at least one liquid bi-functional epoxy resin containing about 40˜50 weight % of aromatic ring; (b) about 55˜120 parts by weight of a curing agent comprising at least one bi-functional thiol curing agent containing aromatic ring and at least one aliphatic tetra-functional thiol curing agent, wherein the curing agent contains about 10˜50 weight % of aromatic ring and about 20˜35 weight % of sulfur; and (c) about 0.05˜0.5 parts by weight of a catalyst. The encapsulant composition having a high refractive index can be used for a solid state light emitting device to enhance light extraction efficiency.

Abstract: A chip package structure and a process for fabricating the same is disclosed. The chip package structure mainly comprises a carrier, a chip and an encapsulating material layer. To fabricate the chip package, a carrier and a plurality of chips are provided. Each chip has at least an active surface with a plurality of bumps thereon. The chips and the carrier are electrically connected. An encapsulating material layer that fills the bonding gap between the chips and the carriers and covers the chips and carrier is formed. The encapsulating material layer between the chips and the carrier has a first thickness and the encapsulating material layer over the chips has a second thickness. The second thickness has a value between half to twice the first thickness.

Abstract: A process for fabricating a chip package structure is disclosed. To fabricate the chip package structure, a carrier and a plurality of chips are provided. Each chip has an active surface and at least one of the active surfaces has a plurality of bumps thereon. The chips and the carrier are electrically connected together. Thereafter, a heat sink is attached to the back of the chips and then at least one heat-resistant buffering film is formed over part of the heat sink surface. An encapsulating material layer is formed over the carrier and filling bonding gaps between the chips and the carrier. The encapsulating material within the bonding gaps has a thickness. The maximum diameter of particles constituting the encapsulating material layer is less than half of the said thickness.

Abstract: A chip package structure and a process for fabricating the same is disclosed. The chip package structure mainly comprises a carrier, a chip and an encapsulating material layer. To fabricate the chip package, a carrier and a plurality of chips are provided. Each chip has at least an active surface with a plurality of bumps thereon. The chips and the carrier are electrically connected. An encapsulating material layer that fills the bonding gap between the chips and the carriers and covers the chips and carrier is formed. The encapsulating material layer between the chips and the carrier has a first thickness and the encapsulating material layer over the chips has a second thickness. The second thickness has a value between half to twice the first thickness.

Abstract: A chip package structure is disclosed. The chip package structure essentially comprises a carrier, one or more chips, a heat sink and an encapsulating material layer. At least one of the chips is flip-chip bonded and electrically connected to the carrier or another chip. There is a flip-chip bonding gap between the chip and the carrier or other chips. A heat sink is positioned on the uppermost chip. The encapsulating material layer fills the flip-chip bonding gap as well as a gap between the uppermost chip and the heat sink. A part of the surface of the heat sink away from the upper-most chip is exposed. Furthermore, the encapsulating material layer is formed in a simultaneous molding process. For example, the chip is separated from the heat sink by a distance between 0.03˜0.2 mm, and the encapsulating material has a thermal conductivity greater than 1.2 W/m.K.

Abstract: A chip package structure is disclosed. The chip package structure essentially comprises a carrier, one or more chips, a heat sink and an encapsulating material layer. At least one of the chips is bonded and electrically connected to the carrier or another chip using a flip-chip bonding technique. A flip-chip bonding gap is set up between the chip and he carrier or other chips. The heat sink is set up over the top chip. The heat sink has an area bigger than the chip. The encapsulating material layer fills up the flip-chip bonding gap and covers the carrier as well as the heat sink. The encapsulating material layer is formed in a simultaneous molding process and has a thermal conductivity more than 1.2 W/m.K. Furthermore, a plurality of standoff components may be selectively positioned on the heat sink.

Abstract: A chip package structure and a process for fabricating the same is disclosed. The chip package structure mainly comprises a carrier, a chip and an encapsulating material layer. To fabricate the chip package, a carrier and a plurality of chips are provided. Each chip has at least an active surface with a plurality of bumps thereon. The chips and the carrier are electrically connected. An encapsulating material layer that fills the bonding gap between the chips and the carriers and covers the chips and carrier is formed. The encapsulating material layer between the chips and the carrier has a first thickness and the encapsulating material layer over the chips has a second thickness. The second thickness has a value between half to twice the first thickness.

Abstract: Fine conductive particles are composed of metallic conductive powder, and an insulating organic capping layer on the grains of the powder. The metallic conductive powder have grains with a diameter ranging from 1 to 20 microns, and the capping layer has a thickness of 50-400 nm, which is able to flow by thermo-pressing. The insulating organic capping layer is prepared from a silane having a reactive functionality, a fluorine-containing silane and a compound or a resin having a functionality able to reactive with the reactive functionality.

Abstract: A method of assembling a semiconductor device forming an encapsulant. The method includes providing a substrate having a plurality of semiconductor devices, respectively connecting a semiconductor chip electrically to a predetermined encapsulation area on a surface of the substrate, filling an encapsulant overlying the predetermined encapsulation area using stencil printing, sweeping excess encapsulant over the predetermined encapsulation area at a first air pressure below approximately 1 atm, sweeping encapsulant overlying the predetermined encapsulation area over the encapsulant overlying the predetermined encapsulation area using stencil printing at a second air pressure above the first air pressure, and hardening the encapsulant at a third air pressure above approximately 1 atm.

Abstract: A chip package structure is disclosed. The chip package structure essentially comprises a carrier, one or more chips, a heat sink and an encapsulating material layer. At least one of the chips is bonded and electrically connected to the carrier or another chip using a flip-chip bonding technique. A flip-chip bonding gap is set up between the chip and he carrier or other chips. The heat sink is set up over the top chip. The heat sink has an area bigger than the chip. The encapsulating material layer fills up the flip-chip bonding gap and covers the carrier as well as the heat sink. The encapsulating material layer is formed in a simultaneous molding process and has a thermal conductivity more than 1.2 W/m.K. Furthermore, a plurality of standoff components may be selectively positioned on the heat sink.

Abstract: A chip package structure and a process for fabricating the same is disclosed. The chip package structure essentially comprises a carrier, one or more chips, a heat sink and an encapsulating material layer. To fabricate the chip package structure, a carrier and a plurality of chips are provided. Each chip has an active surface and at least one of the active surfaces has a plurality of bumps thereon. The chips and the carrier are electrically connected together. Thereafter, a heat sink is attached to the back of the chips and then at least one heat-resistant buffering film is formed over part of the heat sink surface. An encapsulating material layer is formed over the carrier and filling bonding gaps between the chips and the carrier. The encapsulating material within the bonding gaps has a thickness. The maximum diameter of particles constituting the encapsulating material layer is less than half of the said thickness.

Abstract: A chip package structure is disclosed. The chip package structure essentially comprises a carrier, one or more chips, a heat sink and an encapsulating material layer. At least one of the chips is flip-chip bonded and electrically connected to the carrier or another chip. There is a flip-chip bonding gap between the chip and the carrier or other chips. A heat sink is positioned on the uppermost chip. The encapsulating material layer fills the flip-chip bonding gap as well as a gap between the uppermost chip and the heat sink. A part of the surface of the heat sink away from the upper-most chip is exposed. Furthermore, the encapsulating material layer is formed in a simultaneous molding process. For example, the chip is separated from the heat sink by a distance between 0.03˜0.2 mm, and the encapsulating material has a thermal conductivity greater than 1.2 W/m.K.

Abstract: A method of assembling a semiconductor device forming an encapsulant. The method includes providing a substrate having a plurality of semiconductor devices, respectively connecting a semiconductor chip electrically to a predetermined encapsulation area on a surface of the substrate, filling an encapsulant overlying the predetermined encapsulation area using stencil printing, sweeping excess encapsulant over the predetermined encapsulation area at a first air pressure below approximately 1 atm, sweeping encapsulant overlying the predetermined encapsulation area over the encapsulant overlying the predetermined encapsulation area using stencil printing at a second air pressure above the first air pressure, and hardening the encapsulant at a third air pressure above approximately 1 atm.