Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes nanostructures spaced apart from each other in a first direction and a gate structure formed over and around the nanostructures. The semiconductor structure further includes a gate spacer covering a sidewall of the gate structure and a source/drain structure attached to the nanostructures in a second direction. The semiconductor structure further includes a contact spaced apart from the gate structure by the gate spacer in the second direction and a first conductive structure landing over the gate structure. The semiconductor structure further includes a second conductive structure formed over the gate spacer. In addition, a portion of the second conductive structure is sandwiched between the first conductive structure and the contact.

Abstract: A semiconductor device according to the present disclosure includes a first isolation feature and a second isolation feature, a fin structure extending lengthwise along a first direction and sandwiched between the first isolation feature and the second isolation feature along a second direction perpendicular to the first direction, a first channel member disposed over the first isolation feature, a second channel member disposed over the second isolation feature, and a gate structure disposed over and wrapping around the first channel member and the second channel member.

Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a metal gate stack over a substrate and an epitaxial structure over the substrate. The semiconductor device structure also includes a conductive contact electrically connected to the epitaxial structure. A topmost surface of the metal gate stack is vertically disposed between a topmost surface of the conductive contact and a bottommost surface of the conductive contact. The semiconductor device structure further includes a first conductive via electrically connected to the metal gate stack. The topmost surface of the conductive contact is vertically disposed between a topmost surface of the first conductive via and a bottommost surface of the first conductive via. In addition, the semiconductor device structure includes a second conductive via electrically connected to the conductive contact.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor fin over a substrate, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, first and second dielectric layers over the substrate, and an S/D contact disposed on the epitaxial S/D feature. The first and second dielectric layers have different material compositions. A first sidewall of the epitaxial S/D feature is facing the first dielectric layer, a second sidewall of the epitaxial S/D feature is facing the second dielectric layer, and the S/D contact partially covers a top surface of the epitaxial S/D feature and extends continuously to cover the first sidewall of the epitaxial S/D feature.

Abstract: A package structure is provided. The package structure includes a substrate, a die bonded to the substrate, a lid disposed over the die and the substrate, and an interface structure sandwiched between the die and the lid and including a first thermal interface material disposed at corners of a top surface of the die, and a second thermal interface material disposed a rest of the top surface of the die. A Young's modulus of the first thermal interface material is smaller than a Young's modulus of the second thermal interface material.

Abstract: Disclosed is an ultrasonic transducer array configured to generate ultrasonic waves. The ultrasonic transducer array includes multiple transducers arranged along a first direction. Each of the transducers has multiple grooves arranged along a second direction perpendicular to the first direction. The grooves extends along the first direction. A density of the grooves along the second direction decreases from both ends of the transducer toward a center of the transducer.

Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a chip structure over the wiring substrate. The chip package structure includes a first ring structure over the wiring substrate and surrounding the chip structure, wherein a first coefficient of thermal expansion of the first ring structure is less than a second coefficient of thermal expansion of the wiring substrate. The chip package structure includes an anti-warpage structure over the first ring structure. A third coefficient of thermal expansion of the anti-warpage structure is greater than the first coefficient of thermal expansion of the first ring structure.

Abstract: A method includes bonding a first package and a second package over a package component, adhering a first Thermal Interface Material (TIM) and a second TIM over the first package and the second package, respectively, dispensing an adhesive feature on the package component, and placing a heat sink over and contacting the adhesive feature. The heat sink includes a portion over the first TIM and the second TIM. The adhesive feature is then cured.

Abstract: A semiconductor structure includes a metal gate structure having a gate dielectric layer and a gate electrode. A topmost surface of the gate dielectric layer is above a topmost surface of the gate electrode. The semiconductor structure further includes a conductive layer disposed on the gate electrode of the metal gate structure, the conductive layer having a bottom portion disposed laterally between sidewalls of the gate dielectric layer and a top portion disposed above the topmost surface of the gate dielectric layer. The semiconductor structure further includes a contact feature in direct contact with the top portion of the conductive layer.

Abstract: A temperature sensing device includes a substrate, a first reflective module, a first window cover, and a dual thermopile sensor. The first reflective module is disposed on the substrate, including a first mirror chamber with a narrow field of view (FOV), and the first reflective module focuses a thermal radiation from measured object to a first image plane in the first mirror chamber. The first window cover is disposed on the first reflective module, and the first window cover allows a selected band of the thermal radiation to pass through. The dual thermopile sensor is disposed on the substrate and located in the first mirror chamber, and the dual thermopile sensor senses a temperature data from the first image plane. Additional second reflective module, LED source plus pin hole with same FOV of dual thermopile sensor can illuminate the measured object for ease of placement of object to be heated.

Abstract: A gold finger connector and memory storage device having the same. The gold finger connector includes a connector body; a plurality of ground pins; and at least one signal shielding structures, disposed on a first ground pin of the plurality of ground pins, wherein the at least one first signal shielding structure is connected to the outside of a first side of an extension part of the first ground pin and electrically conducts at least two layers of the first ground pin.

Abstract: The disclosure provides a temperature sensing device including a thermopile sensing assembly with a metal sleeve and a metal grid for blocking microwave from entering the thermopile sensor and influencing temperature detection. The temperature sensing device includes one or more than one thermopile sensing elements, an ambient temperature sensor, a signal processing chip, and an infrared lens providing narrow FOV. When dual thermopile sensing elements are used, one is active unit with narrow FOV for measuring the infrared radiation of the object to be detected, and the other one is a dummy unit for the compensation of the thermal shock to achieve the purpose of accurate temperature detection. The disclosure also provides the visible light source to indicate the sensing area of the thermopile sensor, that may facilitate the user positioning the object to be heated. FOV of the light source is the same with that of the thermopile sensor.

Abstract: A semiconductor structure and the manufacturing method thereof are disclosed. An exemplary semiconductor structure includes a first source/drain contact and a second source/drain contact spaced apart by a gate structure, an etch stop layer (ESL) over the first source/drain contact and the second source/drain contact, a conductive feature disposed in the etch stop layer and in direct contact with the first source/drain contact and the second source/drain contact, a dielectric layer over the etch stop layer, and a contact via extending through the dielectric layer and electrically connected to the conductive feature. By providing the conductive feature, a number of metal lines in an interconnect structure of the semiconductor structure may be advantageously reduced.

Abstract: A semiconductor structure includes a substrate, a device layer over the substrate, an interconnect structure over the device layer, and a first plurality of through vias and a second plurality of through vias extending through the substrate, the device layer, and the interconnect structure. The device layer includes first and second device regions. From a top view, the first device region has a first side facing and spaced apart from a second side of the second device region. From the top view, the first plurality of through vias are disposed along a third side of the first device region opposite to the first side of the first device region, the second plurality of through vias are disposed along a fourth side of the second device region opposite to the second side of the second device region. Each through via has a racetrack shape from the top view.

Abstract: A method includes forming a first device die comprising forming an integrated circuit on a semiconductor substrate; and forming an interconnect structure on the semiconductor substrate. The interconnect structure has a plurality of metal layers. The method further includes bonding a second device die to the first device die, and forming gap-fill regions surrounding the second device die. In a first formation process, a first TSV is formed to penetrate through the semiconductor substrate, wherein the first TSV has a first width. In a second formation process, a second TSV is formed to penetrate through the semiconductor substrate. The second TSV has a second width different from the first width.

Abstract: A virtual reality system includes a head-mounted display device and several tracking devices is disclosed. Each tracking devices includes a camera and a processor. The camera obtains a picture of a human body of a current time point. The processor is configured to: obtain a current predicted 3D pose and a confidence of the current time point according to the picture; determine a previous valid value according to a previous predicted 3D pose and a previous final optimized pose; determine a current valid value according to the previous valid value, the confidence, and the current predicted 3D pose; and output the current predicted 3D pose and the confidence to a main tracking device of the tracking devices according to the current valid value, so as to generate a current final optimized pose.

Abstract: A semiconductor device is provided. The semiconductor device includes a silicon layer over a fin, a doped semiconductor layer over the fin and adjoining the silicon layer, a plurality of channel layers over the silicon layer, a source/drain structure on the doped semiconductor layer and adjoining plurality of channel layers, and a plurality of inner spacers between the plurality of channel layers.

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Abstract: A method includes bonding a first package and a second package over a package component, adhering a first Thermal Interface Material (TIM) and a second TIM over the first package and the second package, respectively, dispensing an adhesive feature on the package component, and placing a heat sink over and contacting the adhesive feature. The heat sink includes a portion over the first TIM and the second TIM. The adhesive feature is then cured.