Abstract: A wearable tracking system is provided. The wearable tracking system includes a wearable device, an external camera, and a processor. The wearable device is adapted to be worn on a body part of a user. The wearable device is configured to detect a body movement of the body part based on a tracking sensor. The external camera is configured to obtain a body image of the body part. The processor is configured to obtain a first moving track of a body moving track of the body part based on the body movement, obtain a second moving track of the body moving track of the body part based on the body image, and determine a body pose of the body part based on the first moving track and the second moving track.

Abstract: A temperature sensing device includes a substrate, a first reflective module, a first window cover, and a dual thermopile sensor. The first reflective module is disposed on the substrate, including a first mirror chamber with a narrow field of view (FOV), and the first reflective module focuses a thermal radiation from measured object to a first image plane in the first mirror chamber. The first window cover is disposed on the first reflective module, and the first window cover allows a selected band of the thermal radiation to pass through. The dual thermopile sensor is disposed on the substrate and located in the first mirror chamber, and the dual thermopile sensor senses a temperature data from the first image plane. Additional second reflective module, LED source plus pin hole with same FOV of dual thermopile sensor can illuminate the measured object for ease of placement of object to be heated.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes nanostructures spaced apart from each other in a first direction and a gate structure formed over and around the nanostructures. The semiconductor structure further includes a gate spacer covering a sidewall of the gate structure and a source/drain structure attached to the nanostructures in a second direction. The semiconductor structure further includes a contact spaced apart from the gate structure by the gate spacer in the second direction and a first conductive structure landing over the gate structure. The semiconductor structure further includes a second conductive structure formed over the gate spacer. In addition, a portion of the second conductive structure is sandwiched between the first conductive structure and the contact.

Abstract: The present invention discloses a computing system for targeting advertising audiences, comprising a user data processing device, a user behavior characteristic processing device and a data packaging device. The user data processing device acquires a plurality set of user data serving as to-be-analyzed overall data. The user behavior characteristic processing device is connected to the user data processing device, and the user behavior characteristic processing device derives a store active visitor set from the to-be-analyzed overall data and a target user group set from the store active visitor set. The data packaging device is connected to the user behavior characteristic processing device, and the data packaging device performs a packaging process on the target user group set to obtain an advertising audience packet and transmits the advertising audience packet to an advertising platform.

Abstract: A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.

Abstract: A camera is configured to obtain camera data which includes a body image of a body portion of a user. An IMU sensor is configured to obtain sensor data and adapted to be mounted on the body portion. A processor is configured to determine the body portion being static or dynamic based on the camera data or the sensor data. In response to the body portion being static, the processor is configured to determine a pose confidence of a current pose of the body portion based on the camera data and calibrate an accumulative error of the sensor data based on the pose confidence and the camera data. In response to the body portion being dynamic, the processor is configured to calibrate the accumulative error based on a first moving track and a second moving track. The processor is configured to track the body portion based on the sensor data.

Abstract: A semiconductor device includes a substrate, a plurality of nanosheets, a plurality of source/drain (S/D) features, and a gate stack. The substrate includes a first fin and a second fin. The first fin has a first width less than a second width of the second fin. The plurality of nanosheets is disposed on the first fin and the second fin. The plurality of source/drain (S/D) features are located on the first fin and the second fin and abutting the plurality of nanosheets. A bottom surface of the plurality of source/drain (S/D) features on the first fin is equal to or lower than a bottom surface of the plurality of source/drain (S/D) features on the second fin. The gate stack wraps each of the plurality of nanosheets.

Abstract: A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.

Abstract: A method includes bonding a first package and a second package over a package component, adhering a first Thermal Interface Material (TIM) and a second TIM over the first package and the second package, respectively, dispensing an adhesive feature on the package component, and placing a heat sink over and contacting the adhesive feature. The heat sink includes a portion over the first TIM and the second TIM. The adhesive feature is then cured.

Abstract: A temperature sensing device includes a substrate, a first reflective module, a first window cover, and a dual thermopile sensor. The first reflective module is disposed on the substrate, including a first mirror chamber with a narrow field of view (FOV), and the first reflective module focuses a thermal radiation from measured object to a first image plane in the first mirror chamber. The first window cover is disposed on the first reflective module, and the first window cover allows a selected band of the thermal radiation to pass through. The dual thermopile sensor is disposed on the substrate and located in the first mirror chamber, and the dual thermopile sensor senses a temperature data from the first image plane. Additional second reflective module, LED source plus pin hole with same FOV of dual thermopile sensor can illuminate the measured object for ease of placement of object to be heated.

Abstract: A transmission device for suppressing the glass-fiber effect includes a circuit board and a transmission line. The circuit board includes a plurality of glass fibers, so as to define a fiber pitch. The transmission line is disposed on the circuit board. The transmission line includes a plurality of non-parallel segments. Each of the non-parallel segments of the transmission line has an offset distance with respect to a reference line. The offset distance is longer than or equal to a half of the fiber pitch.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and nanostructures suspended over the substrate. The semiconductor structure also includes a gate structure wrapping around the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure also includes a contact vertically over the source/drain structure and a first conductive structure vertically over the gate structure. The semiconductor structure also includes a second conductive structure in contact with a top surface of the first conductive structure and a top surface of the contact and including an extending portion laterally sandwiched between the first conductive structure and the contact.

Abstract: An infant care apparatus includes a piezoelectric sensor and an infrared array sensor. The piezoelectric sensor senses a respiration rate and a heart rate of an infant. The infrared array sensor senses a body temperature and an occupancy state of the infant in a non-contact manner. The abovementioned infant care apparatus can assist in determining an abnormality of the respiration rate and the heart rate of the infant based on the occupancy state of the infant output by the infrared array sensor, so as to reduce a false alarm rate.

Abstract: A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.

Abstract: A method for forming a semiconductor device includes forming a metal gate stack having a gate dielectric layer and a gate electrode disposed over the gate dielectric layer. The gate electrode includes a first metal layer and a second metal layer. The method further includes performing a plasma treatment to a top surface of the metal gate stack and forming a conductive layer over the treated top surface of the metal gate stack. A top portion of the conductive layer is formed above a top surface of the gate dielectric layer, and a bottom portion of the conductive layer penetrates into the first and the second metal layers of the gate electrode at different distances.

Abstract: A method of forming a semiconductor structure includes providing a semiconductor substrate having a source/drain feature and a gate structure formed thereon; forming an interlayer dielectric layer on the semiconductor substrate; patterning the interlayer dielectric layer to form a trench to expose the source/drain feature within the trench; forming a dielectric liner on sidewalls of the trench; filling a metal layer in the trench; recessing a portion of the metal layer in the trench, thereby forming a recess in the metal layer; and refilling a dielectric material layer in the recess.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base. The semiconductor device structure includes a first multilayer stack over the base. The first multilayer stack includes a first channel layer and a second channel layer over and spaced apart from the first channel layer. The semiconductor device structure includes a gate stack over the substrate. The gate stack wraps around the first multilayer stack. The semiconductor device structure includes an inner spacer layer between the second channel layer and the first channel layer and between the first channel layer and the base. The semiconductor device structure includes a bottom spacer over the base. The semiconductor device structure includes a first source/drain structure over the bottom spacer and connected to the second channel layer.

Abstract: A method includes bonding a first package and a second package over a package component, adhering a first Thermal Interface Material (TIM) and a second TIM over the first package and the second package, respectively, dispensing an adhesive feature on the package component, and placing a heat sink over and contacting the adhesive feature. The heat sink includes a portion over the first TIM and the second TIM. The adhesive feature is then cured.

Abstract: A semiconductor device is provided. The semiconductor device includes a fin protruding from a semiconductor substrate and a gate structure formed across the fin. The semiconductor device also includes a gate spacer formed over a sidewall of the gate structure. The gate spacer includes a sidewall spacer and a sealing spacer formed above the sidewall spacer. In addition, an air gap is vertically sandwiched between the sidewall spacer and the sealing spacer. The semiconductor device further includes a hard mask formed over the gate structure and covering a sidewall of the sealing spacer.