Abstract: The present invention discloses a trench-type heat sink structure applicable to semiconductor devices. An embodiment of the present invention comprises: a first semiconductor substrate; a heat source including at least one heat spot, in which the heat source is on/in the semiconductor substrate or being a part of the semiconductor substrate; at least one first heat conduction layer; at least one first heat conduction structure configured to connect the at least one heat spot with the at least one first heat conduction layer; at least one heat sink trench; and at least one second heat conduction structure configured to connect the at least one first heat conduction layer with the at least one heat sink trench, so as to transmit heat from the heat source to the at least one heat sink trench.

Abstract: An integrated inductor is disclosed herein. The integrated inductor includes a substrate, an insulation layer, and an inductor. The substrate includes a trench. At least a portion of the insulation layer is formed in the trench. The inductor is disposed in the trench, and the inductor is disposed on the insulation layer.

Abstract: A metal trench de-noise structure includes a trench disposed in a substrate, an insulating layer deposited on the sidewall of the trench, an Inter-Layer Dielectric layer covering the substrate and the insulating layer, and a metal layer penetrating the Inter-Layer Dielectric layer to fill up the trench. The metal layer may be grounded or floating.

Abstract: A transformer includes an input terminal, an output terminal, a first wire, and a second wire. The input and output terminals are disposed at two sides of the transformer with respect to a middle point of the transformer. The two sides of the transformer are opposite to each other. On the basis of a middle line which is disposed between the input terminal and the output terminal and passes through the middle point of the transformer, the two opposite sides include a first side and a second side which are disposed at opposite sides of the middle line. The first wire is winded to form circles. The second wire is winded correspondingly to the first wire to form circles. The first wire and/or the second wire are winded in an interlaced manner at location of the input terminal, location of the output terminal, the first side, and the second side.

Abstract: The present invention provides a semiconductor device, which includes a substrate, a first gate electrode, a second gate electrode, a source region and a drain region, wherein the first gate electrode and the second gate electrode are embedded in the substrate respectively; the source region is formed in the substrate, and at least a portion of the source region is disposed between the first gate electrode and the second gate electrode; and the drain region is formed in the substrate, and at least a portion of the drain region is disposed between the first gate electrode and the second gate electrode.

Abstract: This invention discloses a structure of an integrated inductor, comprising: an outer metal segment which comprises a first metal sub-segment and a second metal sub-segment; an inner metal segment which is arranged inside an area surrounded by the outer metal segment and comprises a third metal sub-segment and a fourth metal sub-segment; and at least a connecting structure for connecting the outer metal segment and the inner metal segment. The first metal sub-segment corresponds to the third metal sub-segment, and the first metal sub-segment and the third metal sub-segment belong to different metal layers in a semiconductor structure. The second metal sub-segment corresponds to the fourth metal sub-segment, and the second metal sub-segment and the fourth metal sub-segment belong to different metal layers in a semiconductor structure.

Abstract: An integrated circuit includes a first inductor, a second inductor, and a blocker. The first inductor is disposed in a metal layer, and the second is disposed in the metal layer. The blocker is disposed on the metal layer and located between the first inductor and the second inductor. The blocker is configured to block coupling occurring between the first inductor and the second inductor.

Abstract: A semiconductor element includes a first spiral coil, a second spiral coil, a connecting section, a first guide segment, and a second guide segment. The first spiral coil is formed with a first end and a second end, and includes a first inner turn and a first outer turn. The first inner turn is located in a range surrounded by the outer turn, and the first end and the second end are located at the first inner turn. The second spiral coil and the first spiral coil are located in substantially a same metal layer. The connecting section connects the first spiral coil and the second spiral coil. The first guide segment is connected to the first end. The second guide segment is connected to the second end. The first guide segment and the second guide segment are fabricated in a metal layer different from a metal layer of the first spiral coil.

Abstract: A semiconductor element fabricated in a semiconductor structure and coupled to an application circuit through at least two connecting terminals. The semiconductor element includes a first spiral coil, a second spiral coil and a connecting portion. The first spiral coil is substantially located in a first metal layer and formed with a first end and a second end. The second spiral coil is substantially located in the first metal layer and formed with a third end and a fourth end. The connecting portion, which is located in a second metal layer, connects the second end and the fourth end. The first end is used as one of the two connecting terminals and the third end is used as the other of the two connecting terminals. The second metal layer is different from the first metal layer.

Abstract: A semiconductor element includes a first coil substantially located at a first plane; a second coil substantially located at the first plane; a connecting section that connects the first coil and the second coil; a third coil substantially located at a second plane different from the first plane; and a fourth coil substantially located at the second plane. The third coil and the first coil are connected through a through structure, and the fourth coil and the second coil are connected through a through structure. The third coil and the fourth are not directly connected.

Abstract: This invention discloses a structure of an integrated inductor, comprising: an outer metal segment which comprises a first metal sub-segment and a second metal sub-segment; an inner metal segment which is arranged inside an area surrounded by the outer metal segment and comprises a third metal sub-segment and a fourth metal sub-segment; and at least a connecting structure for connecting the outer metal segment and the inner metal segment. The first metal sub-segment corresponds to the third metal sub-segment, and the first metal sub-segment and the third metal sub-segment belong to different metal layers in a semiconductor structure. The second metal sub-segment corresponds to the fourth metal sub-segment, and the second metal sub-segment and the fourth metal sub-segment belong to different metal layers in a semiconductor structure.

Abstract: A FinFET that includes a semiconductor substrate that has insulating areas, a fin structure, a gate dielectric layer, a gate electrode structure, a drain structure and a source structure is provided. The fin structure is disposed to extend on the semiconductor substrate between two insulating areas. The gate dielectric layer is disposed to extend across two sides of the fin structure. The gate electrode structure is disposed on the gate dielectric layer. The drain structure is disposed at a first side of the gate electrode structure and has a first resistance relative to the gate electrode. The source structure is disposed at a second side of the gate electrode structure and has a second resistance relative to the gate electrode. The first resistance is larger than the second resistance.

Abstract: A stacked capacitor structure includes a MOS varactor and a stacked capacitor. The stacked capacitor is electrically connected to the MOS varactor. The MOS varactor includes a substrate, a gate, a first source/drain and a second source/drain. The substrate has a well, and the gate is positioned over the well. The first source/drain and the second source/drain are formed in the well and positioned at opposing sides of the gate. The stacked capacitor includes a plurality of metal layers. The metal layers are spaced from each other, stacked above the gate, and positioned below an inductive element.

Abstract: A patterned shield structure applied to an integrated circuit (IC) is disposed between an inductor and a substrate of the integrated circuit. The patterned shield structure includes a center structure unit, a first patterned structure unit, and a second patterned structure unit. The center structure unit includes a first sub-center structure unit and a second sub-center structure unit. The second sub-center structure unit and the first sub-center structure unit are symmetrically disposed with respect to a middle of the center structure unit. The first patterned structure unit is disposed on one side of the center structure unit. The second patterned structure unit is disposed on another side of the center structure unit. The second patterned structure unit and the first patterned structure unit are symmetrically disposed with respect to the center structure unit.

Abstract: An integrated stacked transformer includes a primary winding, a secondary winding and a plurality of bridges, wherein the primary winding is formed by a first metal layer and includes a plurality of segments that are not electrically connected to each other; the secondary winding is form by a second metal layer and includes a plurality of segments that are not electrically connected to each other; the plurality of bridges are formed by a third metal layer. A portion of the bridges is connected to the segments of the primary winding respectively to make the segments of the primary winding form a primary inductor; and another portion of the bridges is connected to the segments of the secondary winding respectively to make the segments of the secondary winding form a secondary inductor.

Abstract: The present invention discloses a trench-type heat sink structure applicable to semiconductor devices. An embodiment of the present invention comprises: a first semiconductor substrate; a heat source including at least one heat spot, in which the heat source is on/in the semiconductor substrate or being a part of the semiconductor substrate; at least one first heat conduction layer; at least one first heat conduction structure configured to connect the at least one heat spot with the at least one first heat conduction layer; at least one heat sink trench; and at least one second heat conduction structure configured to connect the at least one first heat conduction layer with the at least one heat sink trench, so as to transmit heat from the heat source to the at least one heat sink trench.

Abstract: A fin field-effect transistor is provided. The fin field-effect transistor includes a substrate, a fin structure, a gate-stacked structure, and an isolation structure. The fin structure is disposed on the substrate, and the gate-stacked structure covers the fin structure.

Abstract: An integrated inductor includes a patterned ground shield, an inner rail, and an inductor. The patterned ground shield is disposed in a first direction. The inner rail is coupled to the patterned ground shield. The inner rail is disposed inside the integrated inductor and in a second direction. The first direction is perpendicular to the second direction. The inductor is disposed above the patterned ground shield.

Abstract: An electronic apparatus includes an electromagnetic radiation source structure and an electromagnetic radiation suppression structure. The electromagnetic radiation source structure is formed in at least one first semiconductor die. The electromagnetic radiation suppression structure is formed in a second semiconductor die, and is used for generating an inverse electromagnetic radiation against the electromagnetic radiation emission of the electromagnetic radiation source structure by sensing the electromagnetic radiation emission of the electromagnetic radiation source structure, to suppress the electromagnetic radiation emission of the electromagnetic radiation source structure from passing through the electromagnetic radiation suppression structure. Another electronic apparatus includes an electromagnetic radiation source structure and an electromagnetic radiation suppression structure. The electromagnetic radiation suppression structure is formed in a printed circuit board.

Abstract: An integrated stacked transformer includes a primary inductor and a secondary inductor, and the primary inductor includes at least a first turn and a second turn, and is at least formed by a plurality of windings of a first metal layer and a second metal layer, wherein the first metal layer and the second metal layer are two adjacent metal layers, and the second turn of the primary inductor is disposed inside the first turn; the secondary inductor includes at least a first turn, and the secondary inductor is at least formed by at least one winding formed by the second metal layer, wherein the first turn of the secondary inductor substantially overlaps the first turn of the primary inductor; wherein the second turn of the primary inductor includes a segment of a parallel connection structure constructed by the first metal layer and the second metal layer.