Patents by Inventor Hsun-Ying Huang

Hsun-Ying Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240119843
    Abstract: A ship navigation display system is set in a ship and includes a communications device, sensing device, first computing device, second computing device and wearable device. The communications device receives first coordinate information corresponding to a ship. The sensing device senses second coordinate information corresponding to a first ship around the ship. The first computing device is communicably connected with the communications device and calculates a collision probability according to the first and second coordinate information. When the collision probability is greater than a threshold value, the first computing device transmits a collision prediction signal. The second computing device receives the collision prediction signal and projects the second coordinate information corresponding to the first ship to a virtual coordinate in a virtual space.
    Type: Application
    Filed: November 11, 2022
    Publication date: April 11, 2024
    Inventors: Jia Hao Wang, Zhi Ying Chen, Hsun Hui Huang, Chien Der Lin
  • Publication number: 20240088195
    Abstract: An image sensor device includes a semiconductor substrate, a radiation sensing member, a shallow trench isolation, and a color filter layer. The radiation sensing member is in the semiconductor substrate. An interface between the radiation sensing member and the semiconductor substrate includes a direct band gap material. The shallow trench isolation is in the semiconductor substrate and surrounds the radiation sensing member. The color filter layer covers the radiation sensing member.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yu WEI, Yen-Liang LIN, Kuo-Cheng LEE, Hsun-Ying HUANG, Hsin-Chi CHEN
  • Publication number: 20240063234
    Abstract: The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a substrate and a transfer gate disposed from a front-side surface of the substrate. The CMOS image sensor further comprises a photo detecting column disposed at one side of the transfer gate within the substrate. The photo detecting column comprises a doped sensing layer comprising one or more recessed portions along a circumference of the doped sensing layer in parallel to the front-side surface of the substrate. By forming the photo detecting column with recessed portions, a junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.
    Type: Application
    Filed: November 2, 2023
    Publication date: February 22, 2024
    Inventors: Chia-Yu Wei, Hsin-Chi Chen, Kuo-Cheng Lee, Ping-Hao Lin, Hsun-Ying Huang, Yen-Liang Lin, Yu Ting Kao
  • Publication number: 20240038804
    Abstract: An image sensor device is provided. The image sensor device includes a substrate having a front surface, a back surface, and a light-sensing region. The image sensor device includes a first isolation structure extending from the front surface into the substrate. The first isolation structure surrounds a first portion of the light-sensing region, the first isolation structure has an etch stop layer, the etch stop layer has an end portion, and the end portion has an H-like shape. The image sensor device includes a second isolation structure extending into the substrate from the back surface to the end portion. The second isolation structure surrounds a second portion of the light-sensing region.
    Type: Application
    Filed: October 16, 2023
    Publication date: February 1, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Wei CHENG, Chun-Hao CHOU, Kuo-Cheng LEE, Hsun-Ying HUANG
  • Publication number: 20240021645
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method includes forming a first dielectric bonding layer over a first dielectric structure, which is disposed on a first substrate and surrounds a first plurality of interconnects. The first dielectric bonding layer is patterned to form a first recess exposing one of the first plurality of interconnects. A first conductive bonding segment is formed within the first recess. A second dielectric bonding layer is formed over a TSV extending through a second substrate. The second dielectric bonding layer is patterned to form a second recess exposing the TSV. A second conductive bonding segment is formed within the second recess. The first substrate is bonded to the second substrate along an interface comprising dielectric and conductive regions. The conductive region includes a conductive interface between the first and second conductive bonding segments.
    Type: Application
    Filed: July 21, 2023
    Publication date: January 18, 2024
    Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Hsun-Ying Huang, Wei-Chih Weng, Yu-Yang Shen
  • Patent number: 11855118
    Abstract: An image sensor device includes a semiconductor substrate, a radiation sensing member, a device layer, and a color filter layer. The semiconductor substrate has a photosensitive region and an isolation region surrounding the photosensitive region. The radiation sensing member is embedded in the photosensitive region of the semiconductor substrate. The radiation sensing member has a material different from a material of the semiconductor substrate, and an interface between the radiation sensing member and the isolation region of the semiconductor substrate includes a direct band gap material. The device layer is under the semiconductor substrate and the radiation sensing member. The color filter layer is over the radiation sensing member and the semiconductor substrate.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yu Wei, Yen-Liang Lin, Kuo-Cheng Lee, Hsun-Ying Huang, Hsin-Chi Chen
  • Patent number: 11843007
    Abstract: The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a substrate and a transfer gate disposed from a front-side surface of the substrate. The CMOS image sensor further comprises a photo detecting column disposed at one side of the transfer gate within the substrate. The photo detecting column comprises a doped sensing layer comprising one or more recessed portions along a circumference of the doped sensing layer in parallel to the front-side surface of the substrate. By forming the photo detecting column with recessed portions, a junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: December 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Yu Wei, Hsin-Chi Chen, Kuo-Cheng Lee, Ping-Hao Lin, Hsun-Ying Huang, Yen-Liang Lin, Yu Ting Kao
  • Publication number: 20230387172
    Abstract: The present disclosure is directed to anchor structures and methods for forming anchor structures such that planarization and wafer bonding can be uniform. Anchor structures can include anchor layers formed on a dielectric layer surface and anchor pads formed in the anchor layer and on the dielectric layer surface. The anchor layer material can be selected such that the planarization selectivity of the anchor layer, anchor pads, and the interconnection material can be substantially the same as one another. Anchor pads can provide uniform density of structures that have the same or similar material.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yu Wei, Cheng-Yuan Li, Hsin-Chi Chen, Kuo-Cheng Lee, Hsun-Ying Huang, Yen-Liang Lin
  • Publication number: 20230378115
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride.
    Type: Application
    Filed: July 23, 2023
    Publication date: November 23, 2023
    Inventors: Hsin-Chi CHEN, Hsun-Ying HUANG, Chih-Ming LEE, Shang-Yen WU, Chih-An YANG, Hung-Wei HO, Chao-Ching CHANG, Tsung-Wei HUANG
  • Publication number: 20230378205
    Abstract: A semiconductor device includes a plurality of isolation structures, wherein each isolation structure of the plurality of isolation structures is spaced from an adjacent isolation structure of the plurality of isolation structures. The semiconductor device further includes a gate structure. The gate structure includes a first sidewall and a second sidewall angled with respect to the first sidewall. The gate structure further includes a first surface extending between the first sidewall and the second sidewall, wherein a dimension of the gate structure in a first direction is less than a dimension of each of the plurality of isolation structures in the first direction.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Inventors: Chia-Yu WEI, Fu-Cheng CHANG, Hsin-Chi CHEN, Ching-Hung KAO, Chia-Pin CHENG, Kuo-Cheng LEE, Hsun-Ying HUANG, Yen-Liang LIN
  • Patent number: 11824073
    Abstract: An image sensor device is provided. The image sensor device includes a substrate having a front surface, a back surface, and a light-sensing region. The image sensor device includes a first isolation structure extending from the front surface into the substrate. The first isolation structure surrounds a first portion of the light-sensing region, and the first isolation structure has a first end portion in the substrate. The image sensor device includes a second isolation structure extending from the back surface into the substrate. The second isolation structure surrounds a second portion of the light-sensing region, the second isolation structure has a second end portion in the substrate, and the second end portion of the second isolation structure is closer to the front surface of the substrate than the first end portion of the first isolation structure.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: November 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Hsun-Ying Huang
  • Patent number: 11817470
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first plurality of interconnects within a first dielectric structure on a first substrate, and a second plurality of interconnects within a second dielectric structure on a second substrate. A bonding structure is arranged between the first dielectric structure and the second substrate. An inter-tier interconnect structure extends between the first plurality of interconnects and the second plurality of interconnects and through the second substrate. The inter-tier interconnect structure includes a first region having substantially vertical sidewalls extending through the second substrate and a second region surrounded by the bonding structure. The second region contacts a bottom of the first region and has tapered sidewalls.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: November 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Hsun-Ying Huang, Wei-Chih Weng, Yu-Yang Shen
  • Patent number: 11817472
    Abstract: The present disclosure is directed to anchor structures and methods for forming anchor structures such that planarization and wafer bonding can be uniform. Anchor structures can include anchor layers formed on a dielectric layer surface and anchor pads formed in the anchor layer and on the dielectric layer surface. The anchor layer material can be selected such that the planarization selectivity of the anchor layer, anchor pads, and the interconnection material can be substantially the same as one another. Anchor pads can provide uniform density of structures that have the same or similar material.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: November 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yu Wei, Cheng-Yuan Li, Hsin-Chi Chen, Kuo-Cheng Lee, Hsun-Ying Huang, Yen-Liang Lin
  • Patent number: 11784198
    Abstract: A semiconductor device includes a plurality of isolation structures, wherein each isolation structure of the plurality of isolation structures is spaced from an adjacent isolation structure of the plurality of isolation structures in a first direction. The semiconductor device further includes a gate structure. The gate structure includes a top surface; a first sidewall angled at a non-perpendicular angle with respect to the top surface; and a second sidewall angled with respect to the top surface. The gate structure further includes a first horizontal surface extending between the first sidewall and the second sidewall, wherein the first horizontal surface is parallel to the top surface, and a dimension of the gate structure in a second direction, perpendicular to the first direction, is less than a dimension of each of the plurality of isolation structures in the second direction.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: October 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Yu Wei, Fu-Cheng Chang, Hsin-Chi Chen, Ching-Hung Kao, Chia-Pin Cheng, Kuo-Cheng Lee, Hsun-Ying Huang, Yen-Liang Lin
  • Publication number: 20230308755
    Abstract: An image sensor including a semiconductor substrate, a plurality of color filters, a plurality of first lenses and a second lens is provided. The semiconductor substrate includes a plurality of sensing pixels arranged in array, and each of the plurality of sensing pixels respectively includes a plurality of image sensing units and a plurality of phase detection units. The color filters at least cover the plurality of image sensing units. The first lenses are disposed on the plurality of color filters. Each of the plurality of first lenses respectively covers one of the plurality of image sensing units. The second lens is disposed on the plurality of color filters and the second lens covers the plurality of phase detection units.
    Type: Application
    Filed: June 1, 2023
    Publication date: September 28, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Hsin-Chi Chen, Kuo-Cheng Lee, Hsun-Ying Huang
  • Patent number: 11756913
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: September 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Chi Chen, Hsun-Ying Huang, Chih-Ming Lee, Shang-Yen Wu, Chih-An Yang, Hung-Wei Ho, Chao-Ching Chang, Tsung-Wei Huang
  • Patent number: 11706525
    Abstract: An image sensor including a semiconductor substrate, a plurality of color filters, a plurality of first lenses and a second lens is provided. The semiconductor substrate includes a plurality of sensing pixels arranged in array, and each of the plurality of sensing pixels respectively includes a plurality of image sensing units and a plurality of phase detection units. The color filters at least cover the plurality of image sensing units. The first lenses are disposed on the plurality of color filters. Each of the plurality of first lenses respectively covers one of the plurality of image sensing units. The second lens is disposed on the plurality of color filters and the second lens covers the plurality of phase detection units.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: July 18, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Hsin-Chi Chen, Kuo-Cheng Lee, Hsun-Ying Huang
  • Publication number: 20230225099
    Abstract: A semiconductor structure includes a first transistor comprising a first gate structure over a first active region in a substrate. The semiconductor structure further includes a second active region in the substrate. The semiconductor structure further includes a first butted contact. The first butted contact includes a first portion extending in a first direction and overlapping the second active region, and a second portion extending from the first portion, wherein the second portion directly contacts each of a top surface and a sidewall of the first gate structure.
    Type: Application
    Filed: March 15, 2023
    Publication date: July 13, 2023
    Inventors: You Che CHUANG, Chih-Ming LEE, Hsin-Chi CHEN, Hsun-Ying HUANG
  • Publication number: 20230118159
    Abstract: An image sensor device includes a semiconductor substrate, a radiation sensing member, a device layer, and a color filter layer. The semiconductor substrate has a photosensitive region and an isolation region surrounding the photosensitive region. The radiation sensing member is embedded in the photosensitive region of the semiconductor substrate. The radiation sensing member has a material different from a material of the semiconductor substrate, and an interface between the radiation sensing member and the isolation region of the semiconductor substrate includes a direct band gap material. The device layer is under the semiconductor substrate and the radiation sensing member. The color filter layer is over the radiation sensing member and the semiconductor substrate.
    Type: Application
    Filed: December 15, 2022
    Publication date: April 20, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yu WEI, Yen-Liang LIN, Kuo-Cheng LEE, Hsun-Ying HUANG, Hsin-Chi CHEN
  • Patent number: 11610901
    Abstract: A semiconductor structure includes a first transistor comprising a first gate structure over a first active region in a substrate. The semiconductor structure further includes a second active region in the substrate. The semiconductor structure further includes a first butted contact. The butted contact includes a first portion extending in a first direction and overlapping the second active region, and a second portion extending from the first portion in a second direction, different from the first direction, wherein the second portion directly contacts the first gate structure.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: March 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: You Che Chuang, Chih-Ming Lee, Hsin-Chi Chen, Hsun-Ying Huang