Abstract: Provided herein are anti-PD-L1 antibodies and antigen-binding fragments thereof. Also provided are nucleic acids encoding the antibodies, compositions containing the antibodies, and methods of producing the antibodies and using the antibodies for treating or preventing diseases such as cancer, infectious diseases and autoimmune diseases.

Abstract: A backlight module and a display device are provided. A light reflection layer is disposed at a backlight side of a through-hole region. And the light reflection layer is disposed at an inner side of an iron frame. After a reflection surface (i.e., a first light-reflecting region) receiving light from a backlight source, the light is reflected to the backlight side of the through-hole to brighten the backlight side. The first light-reflecting region enables a relatively dark area of the backlight side to obtain stronger reflection light, and enables a relatively bright area of the backlight side to obtain weaker reflection light, so that a brightness is uniformly distributed after the backlight side being brightened, thereby achieving a brightening effect.

Abstract: A backlight module and a display device are provided. A light reflection layer is disposed at a backlight side of a through-hole region. And the light reflection layer is disposed at an inner side of an iron frame. After a reflection surface (i.e., a first light-reflecting region) receiving light from a backlight source, the light is reflected to the backlight side of the through-hole to brighten the backlight side. The first light-reflecting region enables a relatively dark area of the backlight side to obtain stronger reflection light, and enables a relatively bright area of the backlight side to obtain weaker reflection light, so that a brightness is uniformly distributed after the backlight side being brightened, thereby achieving a brightening effect.

Abstract: A method of fabricating ultra-thin chips is provided. The method includes patterning circuit elements onto a substrate such that sections of the substrate are exposed and etching trenches into the sections of the substrate to define pedestals respectively associated with a corresponding circuit element. The method further includes depositing stressor layer material onto the circuit elements and applying handling tape to the stressor layer material. In addition, the method includes at least one of weakening the substrate in a plane defined by base corners of the pedestals and initiating substrate cracking at the base corners of the pedestals to encourage spalling of the pedestals off the substrate.

Abstract: An integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a first plurality of levels. Each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The structure also includes a crack stop area which includes a crack stop structure having a second plurality of levels. The interconnect and crack stop structures have an equal number of levels. A third plurality of the crack stop structure levels include a high modulus layer unique to the respective crack stop structure level as compared to the corresponding interconnect structure level.

Abstract: A data processing method and apparatus are disclosed. The method includes: obtaining R groups of proposal region sequences, where each group of proposal region sequence includes a plurality of proposal regions; invoking a VRPAC instruction to calculate an area of each proposal region in each group of proposal region sequence; for a jth group of proposal region sequence in the R groups of proposal region sequences, invoking a VIOU instruction and a VAADD instruction to determine j suppression matrices of the jth group of proposal region sequence and determine a suppression vector of the jth group of proposal region sequence based on the j suppression matrices; and determining an unsuppressed proposal region based on a suppression vector of each group of proposal region sequence. The method reduces invoked instructions, reduces instruction execution steps, and shortens a time used in NMS calculation.

Abstract: An integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a plurality of levels, each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The IC structure also includes a crack stop area which includes a crack stop structure having an equal plurality of levels as the interconnect structure. Each of the crack stop structure levels includes at least one of the layers of the interconnection structure at a same level. At least one crack stop structure level also includes a high modulus layer unique to the crack stop structure level as compared to the corresponding interconnect structure level.

Abstract: A method for creating an integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a plurality of levels, each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The IC structure also includes a crack stop area which includes a crack stop structure having an equal plurality of levels as the interconnect structure. Each of the crack stop structure levels includes at least one of the layers of the interconnection structure at a same level. At least one crack stop structure level also includes a high modulus layer unique to the crack stop structure level as compared to the corresponding interconnect structure level. In another aspect of the invention, a method for producing the structure is described.

Abstract: Embodiments of the present invention disclose a matrix multiplier, and relate to the field of data computing technologies, so as to divide two matrices into blocks for computation. The matrix multiplier includes: a first memory, a second memory, an operation circuit, and a controller, where the operation circuit, the first memory, and the second memory may perform data communication by using a bus; and the controller is configured to control, according to a preset program or instruction, a first matrix and a second matrix to be divided into blocks, and control the operation circuit to perform a multiplication operation on corresponding blocks in the first memory and the second memory based on block division results of the controller. The matrix multiplier may be configured to perform a multiplication operation on two matrices.

Abstract: A matrix processing method includes: determining a quantity of non-zero elements in a to-be-processed matrix, where the to-be-processed matrix is a one-dimensional matrix; generating a distribution matrix of the to-be-processed matrix, where the distribution matrix is used to indicate a position of a non-zero element in the to-be-processed matrix; combining the quantity of non-zero elements, values of all non-zero elements in the to-be-processed matrix arranged sequentially, and the distribution matrix, to obtain a compressed matrix of the to-be-processed matrix.

Abstract: The present invention relates to the field of data calculation technologies, and discloses an operation accelerator, to reduce time for performing a multiplication operation on two N*N matrices. The operation accelerator includes: a first memory, a second memory, an operation circuit, and a controller. The operation circuit may perform data communication with the first memory and the second memory by using a bus. The operation circuit is configured to: extract matrix data from the first memory and the second memory, and perform a multiplication operation. The controller is configured to control, according to a preset program or instruction, the operation circuit to complete the multiplication operation. The operation accelerator may be configured to perform a multiplication operation on two matrices.

Abstract: An integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a first plurality of levels. Each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The structure also includes a crack stop area which includes a crack stop structure having a second plurality of levels. The interconnect and crack stop structures have an equal number of levels. A third plurality of the crack stop structure levels include a high modulus layer unique to the respective crack stop structure level as compared to the corresponding interconnect structure level.

Abstract: A combined nanofluidic and integrated circuit device includes a semiconductor wafer, which includes a substrate with active circuitry formed in the substrate; an oxide layer deposited adjacent the active circuitry; a stressor film deposited onto or into the oxide layer in sections, wherein the stressor film has a higher coefficient of thermal expansion than the oxide layer has; and a nanochannel formed in the oxide layer between the sections of the stressor film. According to an exemplary embodiment, the nanochannel is formed in the oxide layer by cooling the oxide layer and the stressor film to a fracture propagation temperature that is less than first and second temperatures at which the oxide layer and the stressor film are deposited on the substrate.

Abstract: A method for constructing an advanced crack stop structure is described. An interconnection structure is formed comprised of a plurality of levels. Each level has an interconnect structure section and a crack stop section. In a first level of the interconnection structure, a high modulus layer is formed in the crack stop recess but not the interconnect recess and a barrier layer and a conductive metal layer is formed in both the interconnection recess and the crack stop recess of the first level. In a second level of the interconnection structure and the crack stop structure, a second high modulus layer is formed in the crack stop recess but not the interconnect recess and a barrier layer and a conductive metal layer is formed in both the interconnection recess and the crack stop recess of the second level. The barrier layers and high modulus layers are deposited in different steps.

Abstract: A method for creating an integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a plurality of levels, each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The IC structure also includes a crack stop area which includes a crack stop structure having an equal plurality of levels as the interconnect structure. Each of the crack stop structure levels includes at least one of the layers of the interconnection structure at a same level. At least one crack stop structure level also includes a high modulus layer unique to the crack stop structure level as compared to the corresponding interconnect structure level. In another aspect of the invention, a method for producing the structure is described.

Abstract: An integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a plurality of levels, each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The IC structure also includes a crack stop area which includes a crack stop structure having an equal plurality of levels as the interconnect structure. Each of the crack stop structure levels includes at least one of the layers of the interconnection structure at a same level. At least one crack stop structure level also includes a high modulus layer unique to the crack stop structure level as compared to the corresponding interconnect structure level.

Abstract: A method is provided to supply power to wafer-scale ICs. The method includes receiving a wafer containing ICs placed on the top of the wafer. The wafer has through-silicon vias to provide power from the bottom to the ICs. The method also includes a printed circuit board, which has power rails in a pattern on the top of the printed circuit board, where the rails provide voltage and ground. The method continues with placing metal solder spheres between the bottom of the wafer and the top of the printed circuit board, where the spheres provide connections between the two, and where the spheres are free to move and operate as mechanical springs to resist clamping forces. The method also includes applying clamping pressure to the structure to establish connections by compressing the spheres, where no soldering is required.

Abstract: A matrix and vector multiplication operation method includes obtaining first indication information of a matrix element, reading a matrix element value of a non-zero element from a preset matrix based on the first indication information, and determining a first location mark code of the read matrix element value, obtaining second indication information of a vector element, reading, from input vector data based on the second indication information, a vector element value of a second location mark code corresponding to the first location mark code, and obtaining a multiplication operation value of the matrix element value and the vector element value.

Abstract: An integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a first plurality of levels. Each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The structure also includes a crack stop area which includes a crack stop structure having a second plurality of levels. The interconnect and crack stop structures have an equal number of levels. A third plurality of the crack stop structure levels include a high modulus layer unique to the respective crack stop structure level as compared to the corresponding interconnect structure level. In another aspect of the invention, a method for fabricating the structure is described.

Abstract: An integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a plurality of levels, each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The IC structure also includes a crack stop area which includes a crack stop structure having an equal plurality of levels as the interconnect structure. Each of the crack stop structure levels includes at least one of the layers of the interconnection structure at a same level. At least one crack stop structure level also includes a high modulus layer unique to the crack stop structure level as compared to the corresponding interconnect structure level. In another aspect of the invention, a method for producing the structure is described.