Abstract: Embodiments of an active power switch topology for a switching regulator are provided herein. The embodiments of the active power switch topology use two or more active power switches in parallel instead of a single active power switch, as found in conventional implementations. The active power switches are controlled such that they turn-on and -off in a manner that reduces parasitic voltage spikes associated with conventional switching regulators, while not degrading efficiency or other parameters associated with the switching regulator. The active power switch topology can be beneficially used within many switching regulators (e.g., buck, boost, or buck-boost) and, in particular, within hard-switched switching regulators that include active power switches integrated on chip.

Abstract: A switching regulator automatically operates in pulse width modulation (“PWM”) mode for high load currents and in burst mode for low load currents. The switching regulator includes a pair of switches to provide a regulated current to a load. The switching regulator further includes a multi-input comparator. A first input of the comparator is coupled to an output of the pair of switches. A second input of the comparator is coupled to a filtered version of the output and a third input is coupled to a reference waveform. The first, second and third inputs of the comparator form a combined input signal to the comparator. An output signal of the comparator is generated by comparing the combined input signal to a threshold of the comparator. The output signal determines a switching frequency of the pair of switches such that the switching frequency is automatically reduced when the load is decreased.