Patents by Inventor Hua-Feng Chen

Hua-Feng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Single stage and scalable serializer
    Patent number: 8514108
    Abstract: According to an exemplary embodiment, a serializer includes upper and lower shift registers configured to perform a load function where parallel input data is loaded from a parallel input bus and a shift function where the parallel input data is shifted to an output register. The upper shift register is configured to perform the load function while the lower shift register performs the shift function, and the lower shift register is configured to perform the load function while the upper shift register performs the shift function. An output register is configured to alternately receive the parallel input data from the upper shift register and the parallel input data from the lower shift register. The upper and lower shift registers and the output register can comprise scan flip-flops.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: August 20, 2013
    Assignee: Broadcom Corporation
    Inventors: Hua-Feng Chen, Karthik Chandrasekharan, Ramamurthy Gorti, Gregory Djaja, Douglas Smith
  • Single Stage and Scalable Serializer
    Publication number: 20120299756
    Abstract: According to an exemplary embodiment, a serializer includes upper and lower shift registers configured to perform a load function where parallel input data is loaded from a parallel input bus and a shift function where the parallel input data is shifted to an output register. The upper shift register is configured to perform the load function while the lower shift register performs the shift function, and the lower shift register is configured to perform the load function while the upper shift register performs the shift function. An output register is configured to alternately receive the parallel input data from the upper shift register and the parallel input data from the lower shift register. The upper and lower shift registers and the output register can comprise scan flip-flops.
    Type: Application
    Filed: May 25, 2011
    Publication date: November 29, 2012
    Applicant: BROADCOM CORPORATION
    Inventors: Hua-Feng Chen, Karthik Chandrasekharan, Ramamurthy Gorti, Gregory Djaja, Douglas Smith