Patents by Inventor Hua Ji

Hua Ji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10717421
    Abstract: A braking force distribution method and system for multiple marshalling train compartments are provided. The method includes: determining a current train compartment of multiple target marshalling train compartments, calculating current axel loads of axels of the current train compartment, and distributing braking forces for the axels of the current train compartment in a positive correlation manner based on the current axel loads of the axels. The braking forces of the axels are distributed by using an axel load compensation technology. A braking force generated by an axle with a small axle load is reduced according to a load-decreasing amount of the axle load, while a braking force generated by an axle with a great axle load is increased according to a load-increasing amount of the axle load, so that the braking forces generated by the axles match the axle loads.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: July 21, 2020
    Assignees: CRRC ZHUZHOU INSTITUTE CO., LTD., ZHUZHOU CRRC TIMES ELECTRIC CO., LTD.
    Inventors: Wenguang Chen, Jing Shang, Xiong Liu, Chaolu Chen, Junfeng Xu, Huishui Peng, Hua Xiao, Wei Li, Bin Zhang, Long Wang, Anhui Ji
  • Publication number: 20200119188
    Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, a first well region formed in a portion of the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type. A second well region is formed in a portion of the first well region, having the first conductivity type. A first gate structure is formed over a portion of the second well region and a portion of the first well region. A first doped region is formed in a portion of the second well region. A second doped region is formed in a portion of the first well region, having the second conductivity type. A second dielectric layer is formed over a portion of the first gate structure, a portion of the first well region, and a portion of the second doped region.
    Type: Application
    Filed: December 11, 2019
    Publication date: April 16, 2020
    Inventors: Cheng-Hua LIN, Yan-Liang JI, Chih-Wen HSIUNG
  • Publication number: 20200077295
    Abstract: A terminal, including: a memory that stores a plurality of instructions; and a processor coupled to the memory and configured to execute the instructions to: multiplex logical channel data of a logical channel group (LCG); and a transmitter configured to transmit a buffer status report (BSR) of a variable length to a network side, wherein the BSR of a variable length contains a first buffer size of the LCG after the logical channel data of the LCG are multiplexed, and the LCG has a second buffer size being greater than zero before the logical channel data of the LCG are multiplexed.
    Type: Application
    Filed: November 7, 2019
    Publication date: March 5, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Yulong SHI, Pengyu JI, Hua ZHOU
  • Publication number: 20200068588
    Abstract: Aspects of the present disclosure relate to methods and apparatus for interference management of wireless links with overriding link priority. The switched wireless link or connection may have lower or higher priority than the non-switched or scheduled link. The priority order between the links may be overridden in certain conditions.
    Type: Application
    Filed: November 5, 2019
    Publication date: February 27, 2020
    Inventors: Hua WANG, Junyi LI, Tingfang JI, Naga BHUSHAN
  • Publication number: 20200044899
    Abstract: The invention provides a method for automatically identifying a modulation mode for a digital communication signal. The method comprises the following steps of: S1: preprocessing a training digital modulation signal; S2: extracting a characteristic value of the training digital modulation signal; S3: constructing a strong classifier by Bagging learning; and S4: preprocessing a modulation signal to be tested and extracting a corresponding characteristic parameter, and then inputting the characteristic parameter into the strong classifier in the S3 to classify and identify the modulation signal. According to the method, by processing all characteristic values in parallel, a success rate of identification has little to do with an identification performance of a single characteristic parameter and is mainly related to an overall performance, so that the identification to the modulation mode has the advantages of fast identification speed and high success rate of identification.
    Type: Application
    Filed: November 30, 2017
    Publication date: February 6, 2020
    Applicant: SOUTH CHINA UNIVERSITY OF TECHNOLOGY
    Inventors: Fangjiong CHEN, Wensong ZHANG, Zeng HU, Fei JI, Hua YU
  • Publication number: 20200034271
    Abstract: A method for log analysis includes receiving log outputs from an application and generating a log file by recording the log outputs in the log file and, for each log output in the log file, attaching a log context record to the log output. The log context record is encoded with a call stack having stack frames and one or more variables in the stack frames. The method further includes grouping the log outputs in the log file based on their log context records.
    Type: Application
    Filed: July 25, 2018
    Publication date: January 30, 2020
    Applicant: VMware, Inc.
    Inventors: Yao ZHANG, Olivier Alain CREMEL, Ming CHEN, Chunyan JI, Jingtao ZHANG, Hua CHEN
  • Patent number: 10542455
    Abstract: A data indication method includes: transmitting a buffer status report to a network side, the buffer status report containing at least one piece of buffer size information, the buffer size information indicating a buffer size to which a logical channel or a logical channel group corresponds; or transmitting a buffer status report of a variable length to a network side; wherein, the buffer status report of a variable length contains buffer size information on a logical channel group with a buffer size being greater than zero when the buffer status report is triggered or before logical channel data are multiplexed, or contains buffer size information on a logical channel group with a buffer size being greater than zero before logical channel data are multiplexed and being equal to zero after the logical channel data are multiplexed.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: January 21, 2020
    Assignee: Fujitsu Limited
    Inventors: Yulong Shi, Pengyu Ji, Hua Zhou
  • Patent number: 10541328
    Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, a first well region formed in a portion of the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type. A second well region is formed in a portion of the first well region, having the first conductivity type. A first gate structure is formed over a portion of the second well region and a portion of the first well region. A first doped region is formed in a portion of the second well region. A second doped region is formed in a portion of the first well region, having the second conductivity type. A second dielectric layer is formed over a portion of the first gate structure, a portion of the first well region, and a portion of the second doped region.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: January 21, 2020
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Hua Lin, Yan-Liang Ji, Chih-Wen Hsiung
  • Publication number: 20200007472
    Abstract: A processing system includes: a first service machine having a first service module; and a first service switch; wherein the first service machine and the first service switch are configured for logically coupling between virtual machines and a virtual switch; wherein the first service machine comprises a first communication interface and a second communication interface, the second communication interface configured for communication with the first service switch.
    Type: Application
    Filed: September 9, 2019
    Publication date: January 2, 2020
    Applicant: HILLSTONE NETWORKS CORP.
    Inventors: Dongyi Jiang, Jin Shang, Ye Zhang, Juxi Li, Hua Ji
  • Patent number: 10506617
    Abstract: Aspects of the present disclosure relate to methods and apparatus for interference management of wireless links with overriding link priority. The switched wireless link or connection may have lower or higher priority than the non-switched or scheduled link. The priority order between the links may be overridden in certain conditions.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: December 10, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Hua Wang, Junyi Li, Tingfang Ji, Naga Bhushan
  • Publication number: 20190371718
    Abstract: A method for manufacturing a semiconductor device includes following operations. A first substrate with a conductive pad is received. A connector is disposed over the conductive pad. A second substrate including a conductive land is provided. A position of the first substrate or the second substrate is adjusted thereby a geometric center of the conductive land is deviated from a geometric center of the connector in a deviated distance. The connector is bonded with the conductive land. A temperature of the semiconductor device is adjusted so as to control elongation of the first substrate and the second substrate, thereby the geometric center of the connector is substantially aligned with the geometric center of the conductive land.
    Type: Application
    Filed: August 13, 2019
    Publication date: December 5, 2019
    Inventors: HUA-WEI TSENG, CHITA CHUANG, MING HUNG TSENG, CHEN-SHIEN CHEN, MIRNG-JI LII
  • Publication number: 20190335357
    Abstract: A data indication method includes: transmitting a buffer status report to a network side, the buffer status report containing at least one piece of buffer size information, the buffer size information indicating a buffer size to which a logical channel or a logical channel group corresponds; or transmitting a buffer status report of a variable length to a network side; wherein, the buffer status report of a variable length contains buffer size information on a logical channel group with a buffer size being greater than zero when the buffer status report is triggered or before logical channel data are multiplexed, or contains buffer size information on a logical channel group with a buffer size being greater than zero before logical channel data are multiplexed and being equal to zero after the logical channel data are multiplexed.
    Type: Application
    Filed: July 8, 2019
    Publication date: October 31, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Yulong SHI, Pengyu JI, Hua ZHOU
  • Patent number: 10419365
    Abstract: A processing system includes: a first service machine having a first service module; and a first service switch; wherein the first service machine and the first service switch are configured for logically coupling between virtual machines and a virtual switch; wherein the first service machine comprises a first communication interface and a second communication interface, the second communication interface configured for communication with the first service switch.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: September 17, 2019
    Assignee: Hillstone Networks Corp.
    Inventors: Dongyi Jiang, Jin Shang, Ye Zhang, Juxi Li, Hua Ji
  • Patent number: 10396904
    Abstract: Disclosed are an adaptive RLS decision feedback equalizing system, characterized by comprising: an error code cross-correlation module, an equalization module, a decision feedback unit, a coefficient updating unit and an autocorrelation estimation module. Also disclosed are an implementation method of the adaptive RLS decision feedback equalizing system, comprising the following steps: 1) setting an initial value of c0 for a filtering coefficient; 2) generating a filtering output signal yk; 3) computing an error code cross-correlation result Ik; 4) updating the filtering coefficient ck?1 to ck; 5) updating an autocorrelation inverse matrix estimation result Pk?1 to Pk according to a forget constant factor w and an equalizer input signal sequence rk; 6) repeating step 2) to step 5), until the equalizer coefficient converges.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: August 27, 2019
    Assignee: SOUTH CHINA UNIVERSITY OF TECHNOLOGY
    Inventors: Fangjiong Chen, Beixiong Zheng, Fei Ji, Hua Yu, Shaoe Lin, Mengna Lou
  • Patent number: 10396166
    Abstract: A semiconductor device capable of high-voltage operation includes a semiconductor substrate having a first conductivity type. A first well doped region is formed in a portion of the semiconductor substrate. The first well doped region has a second conductivity type. A first doped region is formed on the first well doped region, having the second conductivity type. A second doped region is formed on the first well doped region and is separated from the first doped region, having the second conductivity type. A first gate structure is formed over the first well doped region and is adjacent to the first doped region. A second gate structure is formed beside the first gate structure and is close to the second doped region. A third gate structure is formed overlapping a portion of the first gate structure and a first portion of the second gate structure.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: August 27, 2019
    Assignee: MediaTek Inc.
    Inventors: Cheng Hua Lin, Yan-Liang Ji
  • Publication number: 20190250244
    Abstract: Disclosed is an underwater source node positioning method, which includes the specific steps: (1) placing distributed underwater receiving nodes, the source node transmitting a pulse signal, and the receiving nodes receiving the pulse signal sent by the source node; (2) processing the signal of each receiving node; (3) according to a multipath signal received by each receiving node, performing parameter estimation of the position of the source node, specifically: (3-1) calculating a path length of each path; (3-2) calculating a delay difference between each path and a direct path; (3-3) calculating the signal received by each receiving node; (3-4) performing mesh search matching to obtain the position of the source node. Compared with the conventional method, the present invention requires fewer receiving nodes and does not require accurate clock synchronization of signals. The present invention utilizes multipath signals propagated by signals to enable more accurate positioning of the source nodes.
    Type: Application
    Filed: February 7, 2019
    Publication date: August 15, 2019
    Applicant: SOUTH CHINA UNIVERSITY OF TECHNOLOGY
    Inventors: Fei JI, Renzhi BAO, Fangjiong CHEN, Hua YU
  • Patent number: 10373949
    Abstract: A semiconductor device includes a semiconductor substrate and a passive component. The passive component is formed on the semiconductor substrate and includes a first polysilicon (poly) layer, a salicide blockage (SAB) layer and a first salicide layer. The SAB layer is formed on the first poly layer. The first salicide layer is formed on the SAB layer.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: August 6, 2019
    Assignee: MEDIATEK INC.
    Inventors: Yan-Liang Ji, Cheng-Hua Lin, Chih-Chung Chiu
  • Patent number: 9959920
    Abstract: A memory device includes a semiconductor layer with an in-plane polarization component switchable between a first direction and a second direction. A writing electrode is employed to apply a writing voltage to the semiconductor layer to change the in-plane polarization component between the first direction and the second direction. A reading electrode is employed to apply a reading voltage to the semiconductor layer to measure a tunneling current substantially perpendicular to the polarization direction of the in-plane polarization component. The directions of the reading voltage and the writing voltage are substantially perpendicular to each other. Therefore, the reading process is non-destructive. Thin films (e.g., one unit cell thick) of ferroelectric material can be used in the memory device to increase the miniaturization of the device.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: May 1, 2018
    Assignee: Massachusetts Institute of Technology
    Inventors: Junwei Liu, Kai Chang, Shuai-Hua Ji, Xi Chen, Liang Fu
  • Publication number: 20170301385
    Abstract: A memory device includes a semiconductor layer with an in-plane polarization component switchable between a first direction and a second direction. A writing electrode is employed to apply a writing voltage to the semiconductor layer to change the in-plane polarization component between the first direction and the second direction. A reading electrode is employed to apply a reading voltage to the semiconductor layer to measure a tunneling current substantially perpendicular to the polarization direction of the in-plane polarization component. The directions of the reading voltage and the writing voltage are substantially perpendicular to each other. Therefore, the reading process is non-destructive. Thin films (e.g., one unit cell thick) of ferroelectric material can be used in the memory device to increase the miniaturization of the device.
    Type: Application
    Filed: March 8, 2017
    Publication date: October 19, 2017
    Inventors: Junwei LIU, Kai Chang, Shuai-Hua JI, Xi Chen, Liang Fu
  • Publication number: 20160308790
    Abstract: A processing system includes: a first service machine having a first service module; and a first service switch; wherein the first service machine and the first service switch are configured for logically coupling between virtual machines and a virtual switch; wherein the first service machine comprises a first communication interface and a second communication interface, the second communication interface configured for communication with the first service switch.
    Type: Application
    Filed: April 20, 2015
    Publication date: October 20, 2016
    Applicant: Hillstone Networks Corp.
    Inventors: Dongyi Jiang, Jin Shang, Ye Zhang, Juxi Li, Hua Ji