Patents by Inventor Hua Lin

Hua Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250234791
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first electrode over a semiconductor substrate. A data storage element is on the first electrode. A second electrode is over the data storage element. A first spacer layer is on a sidewall of the second electrode. A conductive structure is over the second electrode. The conductive structure includes a first segment adjacent to the sidewall of the second electrode. The first segment extends from an upper surface of the first spacer layer to a first sidewall of the first spacer layer.
    Type: Application
    Filed: April 7, 2025
    Publication date: July 17, 2025
    Inventors: Yao-Wen Chang, Chung-Chiang Min, Harry-Hak-Lay Chuang, Hung Cho Wang, Tsung-Hsueh Yang, Yuan-Tai Tseng, Sheng-Huang Huang, Chia-Hua Lin
  • Publication number: 20250223531
    Abstract: A bionic organ device includes an organ chip and a temperature control module. The organ chip includes a first body, a second body, and a temperature-sensitive film. The temperature-sensitive film is disposed between the first body and the second body, contains hydrophilic polymer material, and forms a flow channel system with the first body and the second body, where the flow channel system includes a first passage and a second passage. The first passage is located between the first body and the temperature-sensitive film, and the second passage is located between the second body and the temperature-sensitive film. The temperature control module includes a thermally conductive material layer and a temperature controller, and the thermally conductive material layer and the hydrophilic polymer material form the temperature-sensitive film. The temperature controller is connected to the thermally conductive material layer and adjusts the temperature of the thermally conductive material layer.
    Type: Application
    Filed: January 9, 2025
    Publication date: July 10, 2025
    Inventors: Ting-Chieh Yang, Pang-Chun Liu, Jui-Hua Lin, Yu-Hsin Wu
  • Publication number: 20250208205
    Abstract: A testing system and a testing method are provided. The testing system includes a movable mechanism, a testing device, a signal source, a nearfield scanner, a CR reflector, and a processor. The testing device is mounted on the movable mechanism and used for emitting or reflecting an electromagnetic wave. The signal source is configured to emit the electromagnetic wave. The nearfield scanner is used for measuring the incoming electromagnetic wave. The CR reflector has a parabolic surface used for reflecting the electromagnetic wave. The processor is coupled to the movable mechanism, the signal source, and the nearfield scanner. The processor is configured to adjust the orientation of the testing device through the movable mechanism, emit the electromagnetic wave through the signal source, and determine the electromagnetic field information of the electromagnetic wave through the nearfield scanner.
    Type: Application
    Filed: October 8, 2024
    Publication date: June 26, 2025
    Applicant: WaveFidelity Inc.
    Inventors: Ike Lin, You-Hua Lin, Chang-Fa Yang, Chang-Lun Liao
  • Patent number: 12322694
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first inter-metal dielectric (IMD) structure disposed over a semiconductor substrate. A metal-insulator-metal (MIM) device is disposed over the first IMD structure. The MIM device includes at least three metal plates that are spaced from one another. The MIM device further includes a plurality of capacitor insulator structures. Each of the plurality of capacitor insulator structures are disposed between and electrically isolate neighboring metal plates of the at least three metal plates.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: June 3, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Hsing-Chih Lin, Kuan-Hua Lin
  • Patent number: 12322742
    Abstract: A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die.
    Type: Grant
    Filed: November 24, 2023
    Date of Patent: June 3, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsiang-Tai Lu, Shuo-Mao Chen, Mill-Jer Wang, Feng-Cheng Hsu, Chao-Hsiang Yang, Shin-Puu Jeng, Cheng-Yi Hong, Chih-Hsien Lin, Dai-Jang Chen, Chen-Hua Lin
  • Publication number: 20250174499
    Abstract: A method of testing a semiconductor package includes: attaching a charge measurement unit to a carrier substrate; forming a first metallization layer over the charge measurement unit, wherein the forming of the first metallization layer induces first charges to accumulate on the charge measurement unit; performing a first test against the charge measurement unit to determine whether breakdown occurs in the charge measurement unit; and in response to determining that no breakdown occurs in the charge measurement unit, forming a second metallization layer over the first metallization layer.
    Type: Application
    Filed: January 23, 2025
    Publication date: May 29, 2025
    Inventors: CHI-HUI LAI, YANG-CHE CHEN, CHEN-HUA LIN, VICTOR CHIANG LIANG, CHWEN-MING LIU
  • Patent number: 12315737
    Abstract: A method for forming a semiconductor structure includes forming a pattern having first and second line features extending in a first direction on a substrate. After depositing a photoresist layer on the substrate to cover the pattern, the photoresist layer is patterned to form a cut pattern including first and second cut features exposing portions of the respective first and second line features. In a top view, at least one of the first and second cut features is asymmetrically arranged with respect to a central axis of a corresponding first or second line feature. At least one angled ion implantation is performed to enlarge the first and second cut features in at least one direction perpendicular to the first direction. The portions of the first and second line features exposed by the respective first and second cut features are then removed.
    Type: Grant
    Filed: May 30, 2023
    Date of Patent: May 27, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzung-Hua Lin, Yi-Ko Chen, Chia-Chu Liu, Hua-Tai Lin
  • Publication number: 20250162859
    Abstract: A MEMS support structure and a cap structure are provided. At least one vertically-extending trench is formed into the MEMS support structure or a portion of the cap structure. A vertically-extending outgassing material portion having a surface that is physically exposed to a respective vertically-extending cavity is formed in each of the at least one vertically-extending trench. A matrix material layer is attached to the MEMS support structure. A movable element laterally confined within a matrix layer is formed by patterning the matrix material layer. The matrix layer is bonded to the cap structure. A sealed chamber containing the movable element is formed. Each vertically-extending outgassing material portion has a surface that is physically exposed to the sealed chamber, and outgases a gas to increase the pressure in the sealed chamber.
    Type: Application
    Filed: January 20, 2025
    Publication date: May 22, 2025
    Inventors: Kuei-Sung Chang, Tai-Bang An, Chun-Wen Cheng, Hung-Hua Lin
  • Publication number: 20250133324
    Abstract: A headphone device of the invention includes a headband, a pair of joining members, a pair of holding members and a pair of sound generating modules. The headband is arc-shaped and has a first end and a second opposite to the first end. The joining members are movably disposed on the headband to approach or apart from the first end and the second end, and each of the joining members includes an upper contact portion extending towards another of the joining member. The holding members are rotatably joined to the joining members respectively, wherein each of the holding members includes a first pivot portion rotatably connected to one of the joining members and a holding portion secured to first pivot portion. The sound generating modules detachably disposed in the holding portion. The holding members rotate between a stretch position and a fold position.
    Type: Application
    Filed: August 9, 2024
    Publication date: April 24, 2025
    Inventors: Tung-Wen TU, Chia-Shuo CHANG, Chi-Tai HO, Ke-Hua LIN
  • Patent number: 12270846
    Abstract: A measuring system and a measuring method of an antenna pattern based on near field to far field transformation (NFTF) are provided. The measuring system includes a probe antenna, a reference antenna, and a control system. The probe antenna measures an electric field radiated by an antenna under test to obtain electric field information. The reference antenna measures the electric field to obtain a reference phase. The control system is coupled to the antenna under test, the probe antenna, and the reference antenna, wherein the control system applies near field focusing to the reference antenna to configure a focus point of the reference antenna on the antenna under test, and the control system performs the NFTF according to the electric field information and the reference phase to output far field patterns.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: April 8, 2025
    Assignee: Chunghwa Telecom Co., Ltd.
    Inventors: Chang-Lun Liao, You-Hua Lin, Jiahn-Wei Lin, Bo-Cheng You, Chang-Fa Yang, De-Xian Song, Wen-Jiao Liao, Yuan-Chang Hou, Tswen-Jiann Huang
  • Patent number: 12274182
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip comprising a memory cell. The memory cell is disposed within a dielectric structure that overlies a substrate. The memory cell comprises a data storage structure disposed between a bottom electrode and a top electrode. An upper conductive structure is disposed in the dielectric structure and on the top electrode. The upper conductive structure comprises a protrusion disposed below an upper surface of the top electrode. A sidewall spacer structure is disposed around the memory cell. The sidewall spacer structure comprises a first sidewall spacer layer around the data storage structure and a second sidewall spacer layer abutting the first sidewall spacer layer. The protrusion contacts the second sidewall spacer layer.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Wen Chang, Chung-Chiang Min, Harry-Hak-Lay Chuang, Hung Cho Wang, Tsung-Hsueh Yang, Yuan-Tai Tseng, Sheng-Huang Huang, Chia-Hua Lin
  • Patent number: 12266312
    Abstract: A display driving system, configured to control a scan operation of a display, comprising: a scan control circuit, configured to receive a start position signal and to generate a switch selecting signal according to the scan start position signal; and a scan switch circuit, coupled to the display and the scan control circuit, and comprising a plurality of switches, configured to turn on one of the switches according to the switch selecting signal, to control the display to start the scan operation at a scan start position; wherein the display comprises N scan lines, wherein the scan start position is one of the scan lines.
    Type: Grant
    Filed: October 23, 2023
    Date of Patent: April 1, 2025
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Wei-Hong Du, Chuan-Chien Hsu, Han-Shui Hsueh, Yen-Hua Lin
  • Patent number: 12255062
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Grant
    Filed: November 14, 2023
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20250084869
    Abstract: An axial-flow heat-dissipation fan including a frame and a blade wheel is provided. The frame has an inlet, an outlet, and an inner wall connected between the inlet and the outlet. The inner wall surrounding the blade wheel has at least one rough region. The blade wheel is rotatably disposed in the frame and located between the inlet and the outlet, and an air flows into the frame via the inlet and flows out of the frame via the outlet by rotation of the blade wheel. A gap exists between a blade end of the blade wheel and the inner wall. A laminar flow is generated at the gap when the blade wheel is rotating and the blade end passes through the rough region so as to prevent a backflow generated at the gap, wherein a flowing direction of the backflow is opposite to a flowing direction of the air flow.
    Type: Application
    Filed: September 11, 2024
    Publication date: March 13, 2025
    Applicant: Acer Incorporated
    Inventors: Cheng-Wen Hsieh, Mao-Neng Liao, Kuang-Hua Lin, Wei-Chin Chen, Tsung-Ting Chen
  • Publication number: 20250089576
    Abstract: A semiconductor structure includes a conductive layer, an IMD layer and a plurality of protrusions. The IMD layer is formed on the conductive layer and has a first etch rate. Each protrusion includes an etching slowing layer, a lower electrode and a MTJ layer, wherein the etching slowing layer is formed on the IMD layer and has a second etch rate, the lower electrode passes through the IMD layer and the etching slowing layer, and the MTJ layer is formed on the lower electrode. The second etch rate is less than the first etch rate.
    Type: Application
    Filed: September 13, 2023
    Publication date: March 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hua LIN, Ming-Che KU, Min-Yung KO, Fu-Ting SUNG, Zhen-Yu GUAN
  • Publication number: 20250087553
    Abstract: A method includes forming a solder layer on a surface of one or more chips. A lid is positioned over the solder layer on each of the one or more chips. Heat and pressure are applied to melt the solder layer and attach each lid to a corresponding solder layer. The solder layer has a thermal conductivity of ?50 W/mK.
    Type: Application
    Filed: November 22, 2024
    Publication date: March 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yang-Che CHEN, Chen-Hua LIN, Huang-Wen TSENG, Victor Chiang LIANG, Chwen-Ming LIU
  • Publication number: 20250079861
    Abstract: A method is to estimate the state of batteries by using a multi-level neural network formed with at least three neural networks. The method comprises steps of: extracting features from the charging and discharging data of a battery through a first-level neural network to form a first-stage output data, and inputting the first-stage output data into a second-level neural network; enhancing local features in the first-stage output data through the second-level neural network to form a second-stage output data; combining the first-stage output data with the second-stage output data to form a combination result to be input into a third-level neural network for data modeling, to generate a state estimation result of the battery. The present invention improves the accuracy of estimation for a flat zone in the charge/discharge curve of the battery, and quickly adjusts the multi-level neural network to achieve accurate estimation of different types of batteries.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 6, 2025
    Applicant: NATIONAL TAIWAN UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Chang-Hua LIN, Jhih-Han DAI, Yi-Xin LIN
  • Publication number: 20250072604
    Abstract: Disclosed is an interlink lock mechanism for multi-layered drawer furniture. A cabinet is provided with the interlink lock mechanism, and the interlink lock mechanism includes a track seat, two fixing assemblies, and a plurality of self-locking adjustment assemblies. Each of the self-locking adjustment assemblies includes a connecting rod, an opening block, and two functional blocks, where a gap between the two fixing assemblies can allow only one opening block to rotatably enter between the two functional blocks or between the functional block and the fixing block. According to the present application, two or more drawers of the cabinet can be prevented from being drawn out at the same time.
    Type: Application
    Filed: October 13, 2023
    Publication date: March 6, 2025
    Applicant: HU HUA METAL PRODUCTS CO.,LTD
    Inventors: Shu Hua LIN, Shu Jiuan LIN, Ping Shun KAO
  • Patent number: 12243788
    Abstract: A method of testing a semiconductor package includes: forming a charge measurement unit over a carrier substrate; forming a first dielectric layer over the charge measurement unit; forming a first metallization layer over the dielectric layer, wherein the forming of the first metallization layer induces first charges to accumulate on the charge measurement unit; performing a first test against the charge measurement unit to determine whether breakdown occurs in the charge measurement unit; and in response to determining that no breakdown occurs in the charge measurement unit, forming a second dielectric layer over the first metallization layer.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chi-Hui Lai, Yang-Che Chen, Chen-Hua Lin, Victor Chiang Liang, Chwen-Ming Liu
  • Publication number: 20250067271
    Abstract: A ventilation system comprises a ventilation fan with a lamp for installing to a ceiling having an installation opening. The ventilation fan comprises a housing, a fan module, a power box, a junction box, a lamp module and a support. The housing has a first opening and an air outlet. The fan module comprises an inlet opening and an outlet opening. The outlet opening communicates with the air outlet. The power box has a first circuit board. The lamp module and the housing are located at opposite sides of the installation opening. The junction box is electrically connected to the first circuit board and the lamp module. The impeller comprises a hub, and a ratio of a height of the hub to a height of the housing is less than 0.5. A ratio of a height of the impeller to a height of the housing is greater than 0.65.
    Type: Application
    Filed: November 12, 2024
    Publication date: February 27, 2025
    Inventors: YU-HSIANG HUANG, YUAN-CHUAN LIU, CHIH-HUA LIN