Patents by Inventor Hua Lin

Hua Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CHIP PACKAGE STRUCTURE WITH CONDUCTIVE SHIELDING FILM
    Publication number: 20240079381
    Abstract: A chip package structure is provided. The chip package structure includes a chip structure. The chip package structure includes a first ground bump below the chip structure. The chip package structure includes a conductive shielding film disposed over the chip structure and extending onto the first ground bump. The conductive shielding film has a concave upper surface facing the first ground bump.
    Type: Application
    Filed: November 9, 2023
    Publication date: March 7, 2024
    Inventors: Chen-Hua YU, An-Jhih SU, Jing-Cheng LIN, Po-Hao TSAI
  • Heteroatom doped polymer nanospheres/carbon nanospheres and preparation method thereof
    Patent number: 11919772
    Abstract: A method to make heteroatom doped polymer nanosphere/carbon nanospheres uses aromatic amine and aldehyde as raw materials, and in the presence of a compound represented by formula I, reacts the aldehyde with the compound represented by formula Ito form a Schiff base, and then reacts the aromatic amine with the resulting Schiff base, wherein the reaction is conducted in an aqueous solution system at a mild reaction temperature (10° C. to 50° C.) under stirring. The resulting polymer nanospheres are subject to centrifugation and drying, followed by calcination in an inert atmosphere to obtain carbon nanospheres. The nanospheres product prepared using the method has controllable dimensions and morphology, an even particle size, and homogeneously doped heteroatoms.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: March 5, 2024
    Assignee: DALIAN UNIVERSITY OF TECHNOLOGY
    Inventors: Rongwen Lu, Minghui Liu, Yingcen Liu, Hua Lin, Caicheng Song
  • Epitaxial structures exposed in airgaps for semiconductor devices
    Patent number: 11923409
    Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Li-Li Su, Wei-Min Liu
  • Semiconductor structure with extended contact structure
    Patent number: 11923413
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure further includes a gate structure surrounding the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure further includes a contact formed over the source/drain structure and extending into the source/drain structure.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon-Jhy Liaw, Chao-Ching Cheng, Hung-Li Chiang, Shih-Syuan Huang, Tzu-Chiang Chen, I-Sheng Chen, Sai-Hooi Yeong
  • Shielding structure for ultra-high voltage semiconductor devices
    Patent number: 11923425
    Abstract: A method for manufacturing a device may include providing an ultra-high voltage (UHV) component that includes a source region and a drain region, and forming an oxide layer on a top surface of the UHV component. The method may include connecting a low voltage terminal to the source region of the UHV component, and connecting a high voltage terminal to the drain region of the UHV component. The method may include forming a shielding structure on a surface of the oxide layer provided above the drain region of the UHV component, forming a high voltage interconnection that connects to the shielding structure and to the high voltage terminal, and forming a metal routing that connects the shielding structure and the low voltage terminal.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Cheng Chiu, Tian Sheng Lin, Hung-Chou Lin, Yi-Min Chen, Chiu-Hua Chung
  • SEMICONDUCTOR DEVICE
    Publication number: 20240072044
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a gate strip, a source doped region and a body doped region. The substrate has an active region. The gate strip is disposed on the substrate within the active region. The gate strip extends along a first direction. The source doped region is located in the active region and adjacent to a first side of the gate strip along the first direction. The body doped region is located in the active region and adjacent to the first side of the gate strip. The body doped region and the source doped region have opposite conductivity types. The body doped region has a first length along a second direction that is different from the first direction, wherein the first length gradually changes along the first direction.
    Type: Application
    Filed: July 26, 2023
    Publication date: February 29, 2024
    Inventors: Cheng-Hua LIN, Yan-Liang JI
  • CONTROL ASSEMBLY
    Publication number: 20240066392
    Abstract: A control assembly includes two controllers and a retractable and foldable mechanism, the retractable and foldable mechanism includes two retractable parts and a central part, and the two controllers are respectively movably connected to two opposite ends of the central part via the two retractable parts.
    Type: Application
    Filed: May 5, 2023
    Publication date: February 29, 2024
    Applicant: DEXIN CORP.
    Inventors: Ho Lung LU, Chin-Lung LIN, Tzu-Hua TSENG
  • COMPLEMENTARY FIELD EFFECT TRANSISTOR WITH CONDUCTIVE THROUGH SUBSTRATE LAYER
    Publication number: 20240072115
    Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.
    Type: Application
    Filed: February 13, 2023
    Publication date: February 29, 2024
    Inventors: Wei-Xiang You, Wei-De Ho, Hsin Yang Hung, Meng-Yu Lin, Hsiang-Hung Huang, Chun-Fu Cheng, Kuan-Kan Hu, Szu-Hua Chen, Ting-Yun Wu, Wei-Cheng Tzeng, Wei-Cheng Lin, Cheng-Yin Wang, Jui-Chien Huang, Szuya Liao
  • METHOD OF FABRICATING MEMORY DEVICE AND PACKAGE STRUCTURE
    Publication number: 20240071953
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • CONTACT PLUGS AND METHODS FORMING SAME
    Publication number: 20240072155
    Abstract: A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.
    Type: Application
    Filed: November 8, 2023
    Publication date: February 29, 2024
    Inventors: Kuo-Hua Pan, Je-Wei Hsu, Hua Feng Chen, Jyun-Ming Lin, Chen-Huang Peng, Min-Yann Hsieh, Java Wu
  • PACKAGE STRUCTURE
    Publication number: 20240071954
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.
    Type: Application
    Filed: November 9, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • INTEGRATED CIRCUIT DEVICE AND METHOD OF FORMING THE SAME
    Publication number: 20240071952
    Abstract: A method includes depositing solder paste over first contact pads of a first package component. Spring connectors of a second package component are aligned to the solder paste. The solder paste is reflowed to electrically and physically couple the spring connectors of the second package component to the first contact pads of the first package component. A device includes a first package component and a second package component electrically and physically coupled to the first package component by way of a plurality of spring coils. Each of the plurality of spring coils extends from the first package component to the second package component.
    Type: Application
    Filed: January 10, 2023
    Publication date: February 29, 2024
    Inventors: Chih-Chiang Tsao, Hsuan-Ting Kuo, Chao-Wei Chiu, Hsiu-Jen Lin, Ching-Hua Hsieh
  • Method for forming package structure with lid
    Patent number: 11915992
    Abstract: A method for forming a package structure is provided, including forming an interconnect structure over a carrier substrate and forming a semiconductor die over a first side of the interconnect structure. A removable film is formed over the semiconductor die. The method includes forming a first stacked die package structure over the first side of the interconnect structure. A top surface of the removable film is higher than a top surface of the first stacked die package structure. The method includes forming a package layer, removing a portion of the package layer to expose a portion of the removable film, removing the removable film to form a recess, forming a lid structure over the semiconductor die and the first stacked die package structure. The lid structure has a main portion and a protruding portion disposed in the recess and extending from the main portion.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shin-Puu Jeng, Po-Yao Lin, Feng-Cheng Hsu, Shuo-Mao Chen, Chin-Hua Wang
  • Electronic system and image aggregation method thereof
    Patent number: 11910103
    Abstract: The application provides an electronic system and an image aggregation method thereof. The electronic system includes a plurality of image pickup devices and an image aggregation device coupled to the image pickup devices. The image aggregation device controls trigger of the image pickup devices. When the image pickup devices are triggered, the image pickup devices pickup a plurality of images and send to the image aggregation device. The image aggregation device flexibly selects the images pickup by the image pickup devices to flexibly aggregate into an aggregated image.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: February 20, 2024
    Assignee: EYS3D MICROELECTRONICS, CO.
    Inventors: Hong-Yeh Hsieh, Ming-Hua Lin
  • Inductive device
    Patent number: 11908884
    Abstract: An inductive device includes an insulating layer, a lower magnetic layer, and an upper magnetic layer that are formed such that the insulating layer does not separate the lower magnetic layer and the upper magnetic layer at the outer edges or wings of the inductive device. The lower magnetic layer and the upper magnetic layer form a continuous magnetic layer around the insulating layer and the conductors of the inductive device. Magnetic leakage paths are provided by forming openings through the upper magnetic layer. The openings may be formed through the upper magnetic layer by semiconductor processes that have relatively higher precision and accuracy compared to semiconductor processes for forming the insulating layer such as spin coating. This reduces magnetic leakage path variation within the inductive device and from inductive device to inductive device.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chou, Yang-Che Chen, Chen-Hua Lin, Victor Chiang Liang, Huang-Wen Tseng, Chwen-Ming Liu
  • GATE DRIVING DEVICE AND OPERATING METHOD FOR GATE DRIVING DEVICE
    Publication number: 20240054937
    Abstract: A gate driving device and an operating method are provided. The gate driving device includes a plurality of gate driving circuits and a control circuit. The gate driving circuits generate a plurality of gate driving signals having different timing. The control circuit is coupled to a plurality of candidate gate driving circuits among the gate driving circuits. The control circuit selects one of the candidate gate driving circuits as an initial stage gate driving circuit per one scanning cycle. A series connection mode between the gate driving circuits is changed in response to a scan selection signal.
    Type: Application
    Filed: August 3, 2022
    Publication date: February 15, 2024
    Applicant: HIMAX TECHNOLOGIES LIMITED
    Inventors: Yen-Hua Lin, Chuan-Chien Hsu, Han-Shui Hsueh, Wei-Hong Du
  • ELECTRONIC PACKAGE STRUCTURE
    Publication number: 20240055417
    Abstract: Provided is an electronic package structure, including a substrate, a first electronic component disposed on the substrate, at least one second electronic component disposed on the substrate, an insulating film disposed on the second electronic component and the substrate, an insulating glue filled onto the second electronic component and the substrate to cover at least part of the insulating film, a liquid metal disposed on the first electronic component, and a heat-dissipating plate disposed on the first electronic component to squeeze the liquid metal. The insulating film and the insulating glue prevent the overflowing liquid metal from contacting the second electronic component and the substrate.
    Type: Application
    Filed: August 10, 2023
    Publication date: February 15, 2024
    Applicant: Acer Incorporated
    Inventors: Yu-Ming Lin, Wen-Neng Liao, Cheng-Wen Hsieh, Kuang-Hua Lin, Wei-Chin Chen
  • Optical lens system
    Patent number: 11899188
    Abstract: An optical lens system includes, in order from a magnified side to a minified side, a first lens group of positive refractive power and a second lens group of positive refractive power. The first lens group includes a first lens and a second lens, and the second lens group includes a third lens and a fourth lens. One of the third lens and the fourth lens includes one aspheric surface, and each of the lenses in the optical lens system is a singlet lens. The optical lens satisfies a condition of TE(?=400)>94%, where TE(?=400) denotes an overall transmittance of all of the lenses in the optical lens system measured at a wavelength of 400 nm.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: February 13, 2024
    Assignee: YOUNG OPTICS INC.
    Inventors: Hung-You Cheng, Yu-Hung Chou, Ching-Lung Lai, Yi-Hua Lin, Wei-Hao Huang
  • SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20240047310
    Abstract: A semiconductor structure includes a molding compound having a first surface and a second surface opposite to the first surface, a passive device component disposed in the molding compound, a via penetrating the molding compound from the first surface to the second surface, a first connection structure disposed over the first surface of the molding compound and electrically coupled to the passive device component, and a second connection structure disposed over the second surface of the molding compound. The first connection structure and the second connection structure are electrically coupled to each other by the via.
    Type: Application
    Filed: October 23, 2023
    Publication date: February 8, 2024
    Inventors: YANG-CHE CHEN, CHEN-HUA LIN, HUANG-WEN TSENG, VICTOR CHIANG LIANG, CHWEN-MING LIU
  • ETCH STOP STRUCTURE FOR IC TO INCREASE STABILITY AND ENDURANCE
    Publication number: 20240021513
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a plurality of conductive contacts overlying a semiconductor substrate. A plurality of first conductive wires is disposed on the plurality of conductive contacts. A plurality of conductive vias overlies the first conductive wires. An etch stop structure is disposed on the first conductive wires. The plurality of conductive vias extend through the etch stop structure. The etch stop structure includes a first etch stop layer, a first insulator layer, and a second etch stop layer. The first insulator layer is disposed between the first etch stop layer and the second etch stop layer.
    Type: Application
    Filed: January 4, 2023
    Publication date: January 18, 2024
    Inventors: Yung-Chang Chang, Lee-Chuan Tseng, Chia-Hua Lin, Shu-Hui Su