Patents by Inventor Hua Liu

Hua Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955460
    Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Da Tsai, Meng-Tse Chen, Sheng-Feng Weng, Sheng-Hsiang Chiu, Wei-Hung Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
  • Patent number: 11953740
    Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
  • Patent number: 11955579
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of light-emitting elements on a first substrate and forming a first pattern array on a second substrate, wherein the first pattern array includes an adhesive layer. The method also includes transferring the plurality of light-emitting elements from the first substrate to the second substrate and forming the first pattern array on a third substrate. The method includes transferring the plurality of light-emitting elements from the second substrate to the third substrate, and reducing an adhesion force of a portion of the adhesive layer. The method also includes forming a second pattern array on a fourth substrate, and transferring the plurality of light-emitting elements from the third substrate to the fourth substrate. The pitch between the plurality of light-emitting elements on the first substrate is different than the pitch of the first pattern array.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: April 9, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Kai Cheng, Tsau-Hua Hsieh, Fang-Ying Lin, Tung-Kai Liu, Hui-Chieh Wang, Chun-Hsien Lin, Jui-Feng Ko
  • Patent number: 11953705
    Abstract: An optical device includes an objective module, a prism module and an ocular module. The prism module includes a first prism, a second prism, a third prism and a first coating. The prism module is disposed between the objective module and the ocular module. A first light beam emitted by an object sequentially passes through the objective module, the prism module and the ocular module. Central axes of the objective module and the ocular module are in parallel without overlapping.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: April 9, 2024
    Assignees: SINTAI OPTICAL (SHENZHEN) CO., LTD., ASIA OPTICAL CO., INC.
    Inventors: Bin Liu, Hua-Tang Liu
  • Patent number: 11955442
    Abstract: In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jiun Yi Wu, Chen-Hua Yu, Chung-Shi Liu
  • Patent number: 11953839
    Abstract: In a method of cleaning a lithography system, during idle mode, a stream of air is directed, through a first opening, into a chamber of a wafer table of an EUV lithography system. One or more particles is extracted by the directed stream of air from surfaces of one or more wafer chucks in the chamber of the wafer table. The stream of air and the extracted one or more particle are drawn, through a second opening, out of the chamber of the wafer table.
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Yu Tu, Shao-Hua Wang, Yen-Hao Liu, Chueh-Chi Kuo, Li-Jui Chen, Heng-Hsin Liu
  • Publication number: 20240113071
    Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.
    Type: Application
    Filed: January 5, 2023
    Publication date: April 4, 2024
    Inventors: Chung-Shi Liu, Mao-Yen Chang, Yu-Chia Lai, Kuo-Lung Pan, Hao-Yi Tsai, Ching-Hua Hsieh, Hsiu-Jen Lin, Po-Yuan Teng, Cheng-Chieh Wu, Jen-Chun Liao
  • Publication number: 20240109803
    Abstract: The present invention provides a flexible glass and manufacturing method thereof. The flexible glass includes a first straight part and a second straight part on two opposite ends thereof, a recess formed between the first straight part and the second straight part, and a pre-bent curve connection part disposed corresponding to the recess. The first straight part and the second straight part are not arranged on the same plane. The flexible glass has a first lateral side and a second lateral side, and the recess sinks from the first lateral side toward the second lateral side. Therefore, the flexible glass is provided with a greater bendability.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: CHENFENG OPTRONICS CORPORATION
    Inventors: CHING-FANG WONG, YU-WEI LIU, WEI-LUN ZENG, KUAN-HUA LIAO
  • Publication number: 20240110565
    Abstract: A rotor assembly, a compressor and an air conditioner. The rotor assembly includes a first rotor, including a first working portion and a second working portion coaxially arranged, wherein the first working portion and the second working portion are rotatable about a first axis; the first working portion includes a plurality of first helical blades, with a first blade groove being formed between adjacent two of the plurality of first helical blades; at least one first air pressure groove is provided on a first end face of the first working portion away from the second working portion; and the first air pressure groove is configured to form a force in a predetermined direction along the first axis when rotating. The rotor assembly can reduce costs of the compressor, simplify structures of moving parts of the compressor, and improve performance and reliability of the compressor.
    Type: Application
    Filed: October 19, 2021
    Publication date: April 4, 2024
    Inventors: Hua Liu, Zhiping Zhang, Xiaokun Wu, Yushi Bi
  • Patent number: 11946845
    Abstract: A method for determining a three-dimensional tortuosity of a loose and broken rock-soil mass, includes the following steps: a particle grading curve of the loose and broken rock-soil mass is obtained by utilizing a particle size analysis, and followed by calculating an equivalent particle size and an average particle size; a porosity of the loose and broken rock-soil mass is obtained by utilizing a moisture content test, a density test, and a specific gravity test; the three-dimensional tortuosity of the loose and broken rock-soil mass is obtained by utilizing the equivalent particle size, the average particle size and the porosity of the loose and broken rock-soil mass. The method has the advantages of simple logic, accuracy and reliability, simple and fast parameter determination, and has high practical value and promotion value in the field of environmental protection and ecological restoration technology.
    Type: Grant
    Filed: November 1, 2023
    Date of Patent: April 2, 2024
    Assignee: KUNMING UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Zhi-quan Yang, Jia-jun Zhang, Jun-fan Xiong, Ying-yan Zhu, Yi Yang, Muhammad Asif Khan, Tian-bing Xiang, Bi-hua Zhang, Han-hua Xu, Jie Zhang, Shen-zhang Liu
  • Patent number: 11947173
    Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
  • Patent number: 11947745
    Abstract: A handwriting data processing method is applied to a pen display having wireless communication function and a data processing device. The handwriting data processing method includes the steps of: the data processing device obtaining a handwriting data from the pen display in a wireless communication manner; the data processing device generating a compressed screen image and transmitting the data of the compressed screen image and the handwriting data, which is not compressed, to the pen display in the wireless communication manner; the pen display uncompressing the data of the compressed screen image and overlapping the uncompressed screen image and the handwriting data to form a complete screen image and displaying the complete screen image. By the handwriting processing method, the machine time of the processor of the pen display is effectively lowered, significantly reducing the delay phenomenon of the displayed handwriting.
    Type: Grant
    Filed: February 16, 2023
    Date of Patent: April 2, 2024
    Assignee: USI ELECTRONICS (SHENZHEN) CO., LTD.
    Inventors: Chih-Hsiang Chen, Chi-Hua Shih, Huang-Chu Liu, Jan-Yi Hsiao
  • Patent number: 11946476
    Abstract: The present disclosure provides a compressor rotor, a compressor and a refrigerant circulation system. The compressor rotor includes: a motor rotor including a plurality of rotor sections, a locking rod, a compression unit rotating part and a locking member. The rotor sections are fixedly connected in an axial direction and are provided with an axial through hole and the locking rod penetrates through the axial through hole. The compression unit rotating part is located at the end part of the motor rotor and is connected to the locking rod. The locking member is configured to lock the compression unit rotating part on the locking rod. The locking rod, the compression unit rotating part and the locking member form a pressing structure which applies a pressure toward an axial inner side to the motor rotor.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: April 2, 2024
    Assignee: Gree Electric Appliances, Inc. of Zhuhai
    Inventors: Hua Liu, Zhiping Zhang, Yuhui Chen, Ruixing Zhong, Hongbo Li, Wenteng Ye, Jingli Qi
  • Patent number: 11949040
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of diodes on a first substrate and forming a first pattern array on a second substrate. The method also includes transferring the plurality of diodes from the first substrate to the second substrate. The method further includes forming the first pattern array on a third substrate. In addition, the method includes transferring the plurality of diodes from the second substrate to the third substrate. The method also includes forming a second pattern array on a fourth substrate. The method further includes transferring the plurality of diodes from the third substrate to the fourth substrate. The pitch between the plurality of diodes on the first substrate is different from the pitch of the first pattern array.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: April 2, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Kai Cheng, Tsau-Hua Hsieh, Fang-Ying Lin, Tung-Kai Liu, Hui-Chieh Wang, Chun-Hsien Lin, Jui-Feng Ko
  • Patent number: 11948051
    Abstract: In one embodiment, a method for auditing the results of a machine learning model includes: retrieving a set of state estimates for original time series data values from a database under audit; reversing the state estimation computation for each of the state estimates to produce reconstituted time series data values for each of the state estimates; retrieving the original time series data values from the database under audit; comparing the original time series data values pairwise with the reconstituted time series data values to determine whether the original time series and reconstituted time series match; and generating a signal that the database under audit (i) has not been modified where the original time series and reconstituted time series match, and (ii) has been modified where the original time series and reconstituted time series do not match.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: April 2, 2024
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Edward R. Wetherbee, Kenneth P. Baclawski, Guang C. Wang, Kenny C. Gross, Anna Chystiakova, Dieter Gawlick, Zhen Hua Liu, Richard Paul Sonderegger
  • Publication number: 20240105504
    Abstract: A semiconductor device includes an insulating base layer, a semiconductor layer, an insulating layer, an isolation trench and a gettering site. The semiconductor layer and the insulating layer are disposed on the insulating base layer in sequence, and the isolation trench is disposed in the semiconductor layer and passes through the insulating layer. The isolation trench includes a first cross-section, a second cross-section and a third cross-section from top to bottom. The first cross-section is higher than the bottom surface of the insulating layer, and the second cross-section and the third cross-section are lower than the bottom surface of the insulating layer. The gettering site is disposed in the semiconductor layer and in contact with the isolation trench, and the vertex of the gettering site is lower than the second cross-section.
    Type: Application
    Filed: September 23, 2022
    Publication date: March 28, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chrong-Jung Lin, Chia-Shen Liu, Wen-Hua Wen
  • Patent number: 11941065
    Abstract: Systems and methods are described for generating record clusters. The methods comprise receiving a plurality of records from data sources and providing at least a subset of the records to a scoring model that determines scores for various pairings of the records, a score for a given pair of the records representing a probability that the given pair of records contain data elements about the same entity. The method further comprises generating a graph data structure that includes a plurality of nodes, individual nodes representing a different record from the records. The method also comprises assigning a different unique identifier to individual clusters of the final clusters and responding to a request for data regarding a given entity by providing aggregated data elements from those records of the records associated with a cluster of the final clusters having an identifier that represents the given entity.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: March 26, 2024
    Assignee: Experian Information Solutions, Inc.
    Inventors: Hua Li, Sophie Liu, Yi He, Zhixuan Wang, Chi Zhang, Kevin Chen, Shanji Xiong, Christer Dichiara, Mason Carpenter, Mark Hirn, Julian Yarkony
  • Patent number: 11942433
    Abstract: In an embodiment, a structure includes: a first integrated circuit die including first die connectors; a first dielectric layer on the first die connectors; first conductive vias extending through the first dielectric layer, the first conductive vias connected to a first subset of the first die connectors; a second integrated circuit die bonded to a second subset of the first die connectors with first reflowable connectors; a first encapsulant surrounding the second integrated circuit die and the first conductive vias, the first encapsulant and the first integrated circuit die being laterally coterminous; second conductive vias adjacent the first integrated circuit die; a second encapsulant surrounding the second conductive vias, the first encapsulant, and the first integrated circuit die; and a first redistribution structure including first redistribution lines, the first redistribution lines connected to the first conductive vias and the second conductive vias.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Jen-Fu Liu, Ming Hung Tseng, Tsung-Hsien Chiang, Yen-Liang Lin, Tzu-Sung Huang
  • Patent number: 11942464
    Abstract: In an embodiment, a method includes: aligning a first package component with a second package component, the first package component having a first region and a second region, the first region including a first conductive connector, the second region including a second conductive connector; performing a first laser shot on a first portion of a top surface of the first package component, the first laser shot reflowing the first conductive connector of the first region, the first portion of the top surface of the first package component completely overlapping the first region; and after performing the first laser shot, performing a second laser shot on a second portion of the top surface of the first package component, the second laser shot reflowing the second conductive connector of the second region, the second portion of the top surface of the first package component completely overlapping the second region.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Jan Pei, Hsiu-Jen Lin, Wei-Yu Chen, Philip Yu-Shuan Chung, Chia-Shen Cheng, Kuei-Wei Huang, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20240096784
    Abstract: Some embodiments of the present disclosure relate to an integrated chip including an extended via that spans a combined height of a wire and a via and that has a smaller footprint than the wire. The extended via may replace a wire and an adjoining via at locations where the sizing and the spacing of the wire are reaching lower limits. Because the extended via has a smaller footprint than the wire, replacing the wire and the adjoining via with the extended via relaxes spacing and allows the size of the pixel to be further reduced. The extended via finds application for capacitor arrays used for pixel circuits.
    Type: Application
    Filed: January 3, 2023
    Publication date: March 21, 2024
    Inventors: Meng-Hsien Lin, Hsing-Chih Lin, Ming-Tsong Wang, Min-Feng Kao, Kuan-Hua Lin, Jen-Cheng Liu, Dun-Nian Yaung, Ko Chun Liu