Patents by Inventor Hua-Shu Wu
Hua-Shu Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11289568Abstract: The present disclosure relates to a MIM (metal-insulator-metal) capacitor having a top electrode overlying a substrate. A passivation layer overlies the top electrode. The passivation layer has a step region that continuously contacts and extends from a top surface of the top electrode to sidewalls of the top electrode. A metal frame overlies the passivation layer. The metal frame continuously contacts and extends from a top surface of the passivation layer to upper sidewalls of the passivation layer in the step region. The metal frame has a protrusion that extends through the passivation layer and contacts the top surface of the top electrode.Type: GrantFiled: May 13, 2019Date of Patent: March 29, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yuan Shih, Kai-Fung Chang, Shih-Fen Huang, Wen-Chuan Tai, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yen-Wen Chen, Anderson Lin, Fu-Chun Huang, Chun-Ren Cheng, Ivan Hua-Shu Wu, Fan Hu, Ching-Hui Lin, Yan-Jie Liao
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Publication number: 20200006469Abstract: The present disclosure relates to a MIM (metal-insulator-metal) capacitor having a top electrode overlying a substrate. A passivation layer overlies the top electrode. The passivation layer has a step region that continuously contacts and extends from a top surface of the top electrode to sidewalls of the top electrode. A metal frame overlies the passivation layer. The metal frame continuously contacts and extends from a top surface of the passivation layer to upper sidewalls of the passivation layer in the step region. The metal frame has a protrusion that extends through the passivation layer and contacts the top surface of the top electrode.Type: ApplicationFiled: May 13, 2019Publication date: January 2, 2020Inventors: Chi-Yuan Shih, Kai-Fung Chang, Shih-Fen Huang, Wen-Chuan Tai, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yen-Wen Chen, Anderson Lin, Fu-Chun Huang, Chun-Ren Cheng, Ivan Hua-Shu Wu, Fan Hu, Ching-Hui Lin, Yan-Jie Liao
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Patent number: 10040681Abstract: A micro electro-mechanical (MEMS) device assembly is provided. The MEMS device assembly includes a first substrate that has a plurality of electronic devices, a plurality of first bonding regions, and a plurality of second bonding regions. The MEMS device assembly also includes a second substrate that is bonded to the first substrate at the plurality of first bonding regions. A third substrate having a recessed region and a plurality of standoff structures is disposed over the second substrate and bonded to the first substrate at the plurality of second bonding regions. The plurality of first bonding regions provide a conductive path between the first substrate and the second substrate and the plurality of the second bonding regions provide a conductive path between the first substrate and the third substrate.Type: GrantFiled: August 20, 2010Date of Patent: August 7, 2018Assignee: Miradia Inc.Inventors: Hua-Shu Wu, Yu-Hao Chien, Shih-Yung Chung, Li-Tien Tseng, Yu-Te Yeh
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Patent number: 9278853Abstract: A manufacturing process of a MEMS device divides a substrate for fabricating a MEMS component into two electrically isolated regions, so that the MEMS component and the circuit disposed on its surface could connect electrically with another substrate below respectively through the corresponding conducing regions, whereby the configuration of the electrical conducting paths and the manufacturing process are simplified. A MEMS device manufactured by using the aforementioned process is also disclosed herein.Type: GrantFiled: April 18, 2014Date of Patent: March 8, 2016Assignee: MiraMEMS Sensing Technology Co., Ltd.Inventors: Yu-Hao Chien, Hua-Shu Wu, Shih-Yung Chung, Li-Tien Tseng, Yu-Te Yeh
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Publication number: 20140227817Abstract: A manufacturing process of a M EMS device divides a substrate for fabricating u MEMS component into two electrically isolated regions, so that the MEMS component and the circuit disposed on its surface could connect electrically with another substrate below respectively through the corresponding conducing regions, whereby the configuration of the electrical conducting paths and the manufacturing process are simplified. A MEMS device manufactured by using the aforementioned process is also disclosed herein.Type: ApplicationFiled: April 18, 2014Publication date: August 14, 2014Applicant: MIRADIA, INC.Inventors: YU-HAO CHIEN, HUA-SHU WU, SHIH-YUNG CHUNG, LI-TIEN TSENG, YU-TE YEH
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Patent number: 8754529Abstract: A MEMS device comprises a substrate for manufacturing a moving MEMS component is divided into two electrically isolated conducting regions to allow the moving MEMS component and a circuit disposed on its surface to connect electrically with another substrate below respectively through their corresponding conducting regions, thereby the electrical conducting paths and manufacturing process can be simplified.Type: GrantFiled: February 21, 2012Date of Patent: June 17, 2014Assignee: Miradia, Inc.Inventors: Yu-Hao Chien, Hua-Shu Wu, Shih-Yung Chung, Li-Tien Tseng, Yu-Te Yeh
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Publication number: 20120248615Abstract: A manufacturing process of a MEMS device divides a substrate for fabricating a MEMS component into two electrically isolated regions, so that the MEMS component and the circuit disposed on its surface could connect electrically with another substrate below respectively through the corresponding conducing regions, whereby the configuration of the electrical conducting paths and the manufacturing process are simplified. A MEMS device manufactured by using the aforementioned process is also disclosed herein.Type: ApplicationFiled: February 21, 2012Publication date: October 4, 2012Applicant: MIRADIA, INC.Inventors: YU-HAO CHIEN, HUA-SHU WU, SHIH-YUNG CHUNG, LI-TIEN TSENG, YU-TE YEH
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Patent number: 8278724Abstract: Methods of fabricating a microelectromechanical structure are provided. An exemplary embodiment of a method of fabricating a microelectromechanical structure comprises providing a substrate. A first patterned sacrificial layer is formed on portions of the substrate, the first patterned sacrificial layer comprises a bulk portion and a protrusion portion. A second patterned sacrificial layer is formed over the first sacrificial layer, covering the protrusion portion and portions of the bulk portion of the first patterned sacrificial layer, wherein the second patterned sacrificial layer does not cover sidewalls of the first patterned sacrificial layer. An element layer is formed over the substrate, covering portions of the substrate, the first patterned sacrificial layer and second patterned sacrificial layer. The first and second patterned sacrificial layers are removed, leaving a microstructure on the substrate.Type: GrantFiled: October 20, 2008Date of Patent: October 2, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Hua Chang, Hua-Shu Wu, Tsung-Mu Lai
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Publication number: 20120146452Abstract: A manufacturing method of the MEMS device disposes a conductive circuit to maintain various elements of the MEMS equi-potential thereby preventing electrostatic damages to various elements of the MEMS during the manufacturing process.Type: ApplicationFiled: November 15, 2011Publication date: June 14, 2012Applicant: MIRADIA, INC.Inventors: HUA-SHU WU, SHIH-YUNG CHUNG, YU-HAO CHIEN, LI-TIEN TSENG, YU-TE YEH
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Patent number: 8119992Abstract: Provided is a system for overlay measurement in semiconductor manufacturing that includes a generator for exposing an overlay target to radiation and a detector for detecting reflected beams of the overlay target. The reflected beams are for overlay measurement and include at least two different beams.Type: GrantFiled: August 7, 2009Date of Patent: February 21, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao-Tzu Lu, Chin-Hsiang Lin, Hua-Shu Wu, Chia-Hsiang Lin, Kuei Shun Chen
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Patent number: 8084361Abstract: A method includes depositing a layer of a sacrificial material in a first region above a substrate. The first region of the substrate is separate from a second region of the substrate, where a corrosion resistant film is to be provided above the second region. The corrosion resistant film is deposited, so that a first portion of the corrosion resistant film is above the sacrificial material in the first region, and a second portion of the corrosion resistant film is above the second region. The first portion of the corrosion resistant film is removed by chemical mechanical polishing. The sacrificial material is removed from the first region using an etching process that selectively etches the sacrificial material, but not the corrosion resistant film.Type: GrantFiled: May 30, 2007Date of Patent: December 27, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Cheng Huang, Hua-Shu Wu, Fa-Yuan Chang, I-Ching Lin, Hsi-Lung Lee, Yuan-Hao Chien
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Patent number: 8049323Abstract: A chip holder formed of silicon, glass, other ceramics or other suitable materials includes a plurality of recesses for retaining semiconductor chips. The bond pads of the semiconductor chip are formed on or over an area of the chip holder that surrounds the semiconductor chip thus expanding the bonding area. The bond pads are coupled, using semiconductor wafer processing techniques, to internal bond pads formed directly on the semiconductor chip.Type: GrantFiled: February 16, 2007Date of Patent: November 1, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Shien Chen, Chao-Hsiang Yang, Jimmy Liang, Han-Liang Tseng, Mirng-Ji Lii, Tjandra Winata Karta, Hua-Shu Wu
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Patent number: 8012785Abstract: An embodiment of a method is provided that includes providing a substrate having a frontside and a backside. A CMOS device is formed on the substrate. A MEMS device is also formed on the substrate. Forming the MEMS device includes forming a MEMS mechanical structure on the frontside of the substrate. The MEMS mechanical structure is then released. A protective layer is formed on the frontside of the substrate. The protective layer is disposed on the released MEMS mechanical structure (e.g., protects the MEMS structure). The backside of the substrate is processed while the protective layer is disposed on the MEMS mechanical structure.Type: GrantFiled: April 24, 2009Date of Patent: September 6, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Chih Liang, Hua-Shu Wu, Li-Chun Peng, Tsung-Cheng Huang, Mingo Liu, Nick Y. M. Shen, Allen Timothy Chang
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Publication number: 20110049652Abstract: A micro electro-mechanical (MEMS) device assembly is provided. The MEMS device assembly includes a first substrate that has a plurality of electronic devices, a plurality of first bonding regions, and a plurality of second bonding regions. The MEMS device assembly also includes a second substrate that is bonded to the first substrate at the plurality of first bonding regions. A third substrate having a recessed region and a plurality of standoff structures is disposed over the second substrate and bonded to the first substrate at the plurality of second bonding regions. The plurality of first bonding regions provide a conductive path between the first substrate and the second substrate and the plurality of the second bonding regions provide a conductive path between the first substrate and the third substrate.Type: ApplicationFiled: August 20, 2010Publication date: March 3, 2011Applicant: Miradia Inc.Inventors: Hua-Shu Wu, Yu-Hao Chien, Shih-Yung Chung, Li-Tien Tseng, Yu-Te Yeh
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Publication number: 20110042827Abstract: A semiconductor structure includes a first substrate and a second substrate bonded over the first substrate. The first substrate includes a passivation layer formed over the first substrate. The passivation layer includes at least one first opening exposing a first bonding pad formed over the first substrate. The second substrate includes at least one second opening aligned with and facing the first opening.Type: ApplicationFiled: November 4, 2010Publication date: February 24, 2011Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Szu Wei LU, Mirng-Ji Lii, Chen-Shien Chen, Hua-Shu Wu, Jerry Tzou
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Patent number: 7851331Abstract: A semiconductor structure includes a first substrate and a second substrate bonded over the first substrate. The first substrate includes a passivation layer formed over the first substrate. The passivation layer includes at least one first opening exposing a first bonding pad formed over the first substrate. The second substrate includes at least one second opening aligned with and facing the first opening.Type: GrantFiled: November 27, 2006Date of Patent: December 14, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Szu Wei Lu, Mirng-Ji Lii, Chen-Shien Chen, Hua-Shu Wu, Jerry Tzou
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Publication number: 20100273286Abstract: An embodiment of a method is provided that includes providing a substrate having a frontside and a backside. A CMOS device is formed on the substrate. A MEMS device is also formed on the substrate. Forming the MEMS device includes forming a MEMS mechanical structure on the frontside of the substrate. The MEMS mechanical structure is then released. A protective layer is formed on the frontside of the substrate. The protective layer is disposed on the released MEMS mechanical structure (e.g., protects the MEMS structure). The backside of the substrate is processed while the protective layer is disposed on the MEMS mechanical structure.Type: ApplicationFiled: April 24, 2009Publication date: October 28, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kai-Chih Liang, Hua-Shu Wu, Li-Chun Peng, Tsung-Cheng Huang, Mingo Liu, Nick Y.M. Shen, Allen Timothy Chang
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Patent number: 7732299Abstract: The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a top metal layer on a first substrate, in which the top metal layer has a plurality of interconnect features and a first dummy feature; forming a first dielectric layer over the top metal layer; etching the first dielectric layer in a target region substantially vertically aligned to the plurality of interconnect features and the first dummy feature of the top metal layer; performing a chemical mechanical polishing (CMP) process over the first dielectric layer; and thereafter bonding the first substrate to a second substrate.Type: GrantFiled: February 12, 2007Date of Patent: June 8, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fa-Yuan Chang, Tsung-Mu Lai, Kai-Chih Liang, Hua-Shu Wu, Chin-Hsiang Ho, Gwo-Yuh Shiau, Chu-Wei Cheng, Ming-Chyi Liu, Yuan-Chih Hsieh, Chia-Shiung Tsai, Nick Y. M. Shen, Ching-Chung Pai
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Patent number: 7728396Abstract: A method and a structure are provided for preventing lift-off of a semiconductor monitor pattern from a substrate. A semiconductor structure and a semiconductor monitor structure are formed on a substrate. A material layer is formed covering the semiconductor monitor structure. A part of the semiconductor structure is removed without removing the semiconductor monitor structure, by using the material layer as an etch protection layer. A mask for the method is also provided. The mask includes a clear area and a dark area. The dark area prevents a semiconductor monitor structure from being subjected to exposure so as to form a material layer covering the semiconductor monitor structure and prevent removal of the semiconductor monitor structure from the substrate while a part of a semiconductor structure is removed.Type: GrantFiled: March 9, 2007Date of Patent: June 1, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hua-Shu Wu, Tsung-Mu Lai, Ming-Chih Chang, Che-Rong Laing
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Patent number: 7696766Abstract: A system and a method of testing a semiconductor die is provided. An embodiment comprises a plurality of tips that each comprise a substrate with a conductive via, a first dielectric layer with vias connected to the conductive via, a second dielectric layer with vias over the first dielectric layer, and a metal layer over the second dielectric layer. Additional dielectric layers with vias may be used. This tip is electrically connected to a redistribution line that routes signals between the tip to electrical connections on a space transformation layer. The space transformation layer is electrically connected to a printed circuit board using, for example, a spring loaded connection such as a pogo pin. The space transformation layer is aligned onto the printed circuit board by a series of guidance mechanisms such as guide pins or smooth fixtures, and the planarity of the tips is adjusted by adjusting the screws.Type: GrantFiled: April 2, 2007Date of Patent: April 13, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsu Ming Cheng, Clinton Chao, Fa-Yuan Chang, Hua-Shu Wu