Patents by Inventor Hua-Shu Wu
Hua-Shu Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090294685Abstract: Provided is a system for overlay measurement in semiconductor manufacturing that includes a generator for exposing an overlay target to radiation and a detector for detecting reflected beams of the overlay target. The reflected beams are for overlay measurement and include at least two different beams.Type: ApplicationFiled: August 7, 2009Publication date: December 3, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiao-Tzu Lu, Chin-Hsiang Lin, Hua-Shu Wu, Chia-Hsiang Lin, Kuei Shun Chen
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Patent number: 7582538Abstract: A method for semiconductor manufacturing includes forming an overlay target having a pattern formed by a first mask layer and an adjacent layer. The overlay target is exposed to radiation. As a result, reflective beams can be detected from the pattern and the adjacent layer and the location of the pattern can be identified based on the reflective beams.Type: GrantFiled: April 6, 2005Date of Patent: September 1, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao-Tzu Lu, Chin-Hsiang Lin, Hua-Shu Wu, Chia-Hsiang Lin, Kuei Shun Chen
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Patent number: 7468327Abstract: Methods of fabricating a microelectromechanical structure are provided. An exemplary embodiment of a method of fabricating a microelectromechanical structure comprises providing a substrate. A first patterned sacrificial layer is formed on portions of the substrate, the first patterned sacrificial layer comprises a bulk portion and a protrusion portion. A second patterned sacrificial layer is formed over the first sacrificial layer, covering the protrusion portion and portions of the bulk portion of the first patterned sacrificial layer, wherein the second patterned sacrificial layer does not cover sidewalls of the first patterned sacrificial layer. An element layer is formed over the substrate, covering portions of the substrate, the first patterned sacrificial layer and second patterned sacrificial layer. The first and second patterned sacrificial layers are removed, leaving a microstructure on the substrate.Type: GrantFiled: June 13, 2006Date of Patent: December 23, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Hua Chang, Hua-Shu Wu, Tsung-Mu Lai
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Publication number: 20080299769Abstract: A method includes depositing a layer of a sacrificial material in a first region above a substrate. The first region of the substrate is separate from a second region of the substrate, where a corrosion resistant film is to be provided above the second region. The corrosion resistant film is deposited, so that a first portion of the corrosion resistant film is above the sacrificial material in the first region, and a second portion of the corrosion resistant film is above the second region. The first portion of the corrosion resistant film is removed by chemical mechanical polishing. The sacrificial material is removed from the first region using an etching process that selectively etches the sacrificial material, but not the corrosion resistant film.Type: ApplicationFiled: May 30, 2007Publication date: December 4, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Cheng Huang, Hua-Shu Wu, Fa-Yuan Chang, I-Ching Lin, Hsi-Lung Lee, Yuan-Hao Chien
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Patent number: 7459344Abstract: The invention provides a method of fabricating a micromachined structure, and in particular to a method of forming a micro-electro-mechanical system (MEMS) structure. A thin silicon cantilevered or suspended structure used to make micromachined structures is first formed from a SOI wafer or a bulk silicon wafer, followed by formation of the micromachined structures by semiconductor manufacturing techniques.Type: GrantFiled: August 10, 2006Date of Patent: December 2, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Hua Chang, Hua-Shu Wu
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Patent number: 7453127Abstract: A double-diffused-drain metal-oxide-semiconductor device has a gate structure overlying a semiconductor substrate, a pair of insulator spacers on the sidewalls of the gate structure respectively, and a pair of floating non-insulator spacers embedded in the pair of insulator spacers respectively.Type: GrantFiled: February 13, 2006Date of Patent: November 18, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hua-Shu Wu, Feng-Chi Hung, Hung-Lin Chen, Shih-Chin Lee
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Publication number: 20080197473Abstract: A chip holder formed of silicon, glass, other ceramics or other suitable materials includes a plurality of recesses for retaining semiconductor chips. The bond pads of the semiconductor chip are formed on or over an area of the chip holder that surrounds the semiconductor chip thus expanding the bonding area. The bond pads are coupled, using semiconductor wafer processing techniques, to internal bond pads formed directly on the semiconductor chip.Type: ApplicationFiled: February 16, 2007Publication date: August 21, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Shien Chen, Chao-Hsiang Yang, Jimmy Liang, Han-Liang Tseng, Mirng-Ji Lii, Tjandra Winata Karta, Hua-Shu Wu
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Publication number: 20080194076Abstract: The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a top metal layer on a first substrate, in which the top metal layer has a plurality of interconnect features and a first dummy feature; forming a first dielectric layer over the top metal layer; etching the first dielectric layer in a target region substantially vertically aligned to the plurality of interconnect features and the first dummy feature of the top metal layer; performing a chemical mechanical polishing (CMP) process over the first dielectric layer; and thereafter bonding the first substrate to a second substrate.Type: ApplicationFiled: February 12, 2007Publication date: August 14, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fa-Yuan Chang, Tsung-Mu Lai, Kai-Chih Liang, Hua-Shu Wu, Chin-Hsiung Ho, Gwo-Yuh Shiau, Chu-Wei Chang, Ming-Chyi Liu, Yuan-Chih Hsieh, Chia-Shiung Tsai, Nick Y. M. Shen, Ching-Chung Pai
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Publication number: 20080180123Abstract: A system and a method of testing a semiconductor die is provided. An embodiment comprises a plurality of tips that each comprise a substrate with a conductive via, a first dielectric layer with vias connected to the conductive via, a second dielectric layer with vias over the first dielectric layer, and a metal layer over the second dielectric layer. Additional dielectric layers with vias may be used. This tip is electrically connected to a redistribution line that routes signals between the tip to electrical connections on a space transformation layer. The space transformation layer is electrically connected to a printed circuit board using, for example, a spring loaded connection such as a pogo pin. The space transformation layer is aligned onto the printed circuit board by a series of guidance mechanisms such as guide pins or smooth fixtures, and the planarity of the tips is adjusted by adjusting the screws.Type: ApplicationFiled: April 2, 2007Publication date: July 31, 2008Inventors: Hsu Ming Cheng, Clinton Chao, Fa-Yuan Chang, Hua-Shu Wu
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Publication number: 20080122114Abstract: A semiconductor structure includes a first substrate and a second substrate bonded over the first substrate. The first substrate includes a passivation layer formed over the first substrate. The passivation layer includes at least one first opening exposing a first bonding pad formed over the first substrate. The second substrate includes at least one second opening aligned with and facing the first opening.Type: ApplicationFiled: November 27, 2006Publication date: May 29, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Szu Wei Lu, Mirng-Ji Lii, Chen-Shien Chen, Hua-Shu Wu, Jerry Tzou
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Publication number: 20080038859Abstract: The invention provides a method of fabricating a micromachined structure, and in particular to a method of forming a micro-electro-mechanical system (MEMS) structure. A thin silicon cantilevered or suspended structure used to make micromachined structures is first formed from a SOI wafer or a bulk silicon wafer, followed by formation of the micromachined structures by semiconductor manufacturing techniques.Type: ApplicationFiled: August 10, 2006Publication date: February 14, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Hua Chang, Hua-Shu Wu
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Publication number: 20080018350Abstract: An interposer for converting pitches includes an interconnect structure over the semiconductor substrate, an active circuit formed on the semiconductor substrate, wherein the active circuit is electrically connected to the interconnect structure, a first plurality of pads with a first pitch over the interconnect structure, a second plurality of pads underlying the semiconductor substrate, and a plurality of through-substrate vias in the semiconductor substrate, wherein the first and the second plurality of pads are interconnected through the plurality of through-substrate vias.Type: ApplicationFiled: September 22, 2006Publication date: January 24, 2008Inventors: Clinton Chao, Chih-Hsien Chang, John C.Y. Chiang, Mark Shane Peng, Hua-Shu Wu, Kim Chen, Wen-Hung Wu, Tjandra Winada Karta
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Publication number: 20070287213Abstract: Methods of fabricating a microelectromechanical structure are provided. An exemplary embodiment of a method of fabricating a microelectromechanical structure comprises providing a substrate. A first patterned sacrificial layer is formed on portions of the substrate, the first patterned sacrificial layer comprises a bulk portion and a protrusion portion. A second patterned sacrificial layer is formed over the first sacrificial layer, covering the protrusion portion and portions of the bulk portion of the first patterned sacrificial layer, wherein the second patterned sacrificial layer does not cover sidewalls of the first patterned sacrificial layer. An element layer is formed over the substrate, covering portions of the substrate, the first patterned sacrificial layer and second patterned sacrificial layer. The first and second patterned sacrificial layers are removed, leaving a microstructure on the substrate.Type: ApplicationFiled: June 13, 2006Publication date: December 13, 2007Inventors: Chia-Hua Chang, Hua-Shu Wu, Tsung-Mu Lai
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Patent number: 7295374Abstract: A method of manufacturing a micro-lens is disclosed. The method includes providing a convex photoresist surface, forming a lens mold on the convex photoresist surface, removing the lens mold from the convex photoresist surface, forming a micro-lens in the lens mold and removing the micro-lens from the lens mold.Type: GrantFiled: February 25, 2005Date of Patent: November 13, 2007Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Ming-Chih Chang, Hua-Shu Wu, Tsung-Mu Lai
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Publication number: 20070187784Abstract: A double-diffused-drain metal-oxide-semiconductor device has a gate structure overlying a semiconductor substrate, a pair of insulator spacers on the sidewalls of the gate structure respectively, and a pair of floating non-insulator spacers embedded in the pair of insulator spacers respectively.Type: ApplicationFiled: February 13, 2006Publication date: August 16, 2007Inventors: Hua-Shu Wu, Feng-Chi Hung, Hung-Lin Chen, Shih-Chin Lee
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Patent number: 7255425Abstract: An ink-ejection unit of an inkjet printhead integrates an ink-channel wafer onto a CMOS wafer with a heating element fabricated therein. A nozzle film with a nozzle orifice is formed on the backside of the CMOS wafer, which allows two-dimensional ink ejecting from the backside of the CMOS wafer.Type: GrantFiled: December 2, 2004Date of Patent: August 14, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Mu Lai, Hua-Shu Wu, Ming-Chih Chang
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Publication number: 20070145366Abstract: A method and a structure are provided for preventing lift-off of a semiconductor monitor pattern from a substrate . A semiconductor structure and a semiconductor monitor structure are formed on a substrate. A material layer is formed covering the semiconductor monitor structure. A part of the semiconductor structure is removed without removing the semiconductor monitor structure, by using the material layer as an etch protection layer. A mask for the method is also provided. The mask includes a clear area and a dark area. The dark area prevents a semiconductor monitor structure from being subjected to exposure so as to form a material layer covering the semiconductor monitor structure and prevent removal of the semiconductor monitor structure from the substrate while a part of a semiconductor structure is removed.Type: ApplicationFiled: March 9, 2007Publication date: June 28, 2007Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hua-Shu Wu, Tsung-Mu Lai, Ming-Chih Chang, Che-Rong Laing
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Patent number: 7198975Abstract: A method and a structure are provided for preventing lift-off of a semiconductor monitor pattern from a substrate. A semiconductor structure and a semiconductor monitor structure are formed on a substrate. A material layer is formed covering the semiconductor monitor structure. A part of the semiconductor structure is removed without removing the semiconductor monitor structure, by using the material layer as an etch protection layer. A mask for the method is also provided. The mask includes a clear area and a dark area. The dark area prevents a semiconductor monitor structure from being subjected to exposure so as to form a material layer covering the semiconductor monitor structure and prevent removal of the semiconductor monitor structure from the substrate while a part of a semiconductor structure is removed.Type: GrantFiled: December 21, 2004Date of Patent: April 3, 2007Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Hua-Shu Wu, Tsung-Mu Lai, Ming-Chih Chang, Che-Rong Laing
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Publication number: 20060228816Abstract: A method for semiconductor manufacturing includes forming an overlay target having a pattern formed by a first mask layer and an adjacent layer. The overlay target is exposed to radiation. As a result, reflective beams can be detected from the pattern and the adjacent layer and the location of the pattern can be identified based on the reflective beams.Type: ApplicationFiled: April 6, 2005Publication date: October 12, 2006Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao-Tzu Lu, Chin-Hsiang Lin, Hua-Shu Wu, Chia-Hsiang Lin, Kuei Chen
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Publication number: 20060193054Abstract: A method of manufacturing a micro-lens is disclosed. The method includes providing a convex photoresist surface, forming a lens mold on the convex photoresist surface, removing the lens mold from the convex photoresist surface, forming a micro-lens in the lens mold and removing the micro-lens from the lens mold.Type: ApplicationFiled: February 25, 2005Publication date: August 31, 2006Inventors: Ming-Chih Chang, Hua-Shu Wu, Tsung-Mu Lai