Abstract: An optical component is provided. The optical component includes a silicon-based body including a bottom wall, a first side wall, a second side wall, and a micro lens structure. The first side wall is located on a first side of the silicon-based body and perpendicular to the bottom wall. The second side wall is located on a second side of the silicon-based body opposite to the first side, and forms an acute angle with the bottom wall. The micro lens structure is formed on the first side wall. The optical component further includes a protection layer formed over the first side wall and the micro lens structure.

Abstract: A method is provided. The method includes: obtaining a first sample dataset; inputting at least one first question text corresponding to at least one piece of first sample data into a dialog model separately to obtain at least one first answer prediction result; inputting each second question text into the dialog model to obtain a second answer prediction result output by the dialog model; inputting the second answer prediction result into a reward model to obtain a score of the second answer prediction result output by the reward model; determining a comprehensive loss based on the at least one first answer prediction result, a first answer text of each of the at least one piece of first sample data, and a score corresponding to each of at least one piece of second sample data; and adjusting at least one parameter of the dialog model based on the comprehensive loss.

Abstract: A biological detection chip includes a base, multiple microstructures, a conducting layer, and a nano metal layer, wherein the base is provided with a surface; the multiple microstructures are arranged on the surface; and each of the microstructures protrudes out of the surface, and is provided with a first inclined plane and a second inclined plane inclining towards each other. The conducting layer covers the surface and the multiple microstructures, and the nano metal layer covers the conducting layer. The biological detection chip may increase the number of antibodies attached to the nano metal layer, so that the detection efficiency is improved.

Abstract: An integrated fan out package is utilized in which the dielectric materials of different redistribution layers are utilized to integrate the integrated fan out package process flows with other package applications. In some embodiments an Ajinomoto or prepreg material is utilized as the dielectric in at least some of the overlying redistribution layers.

Abstract: An extreme ultraviolet (EUV) photolithography system generates EUV light by irradiating droplets with a laser. The system includes a droplet generator with a nozzle and a piezoelectric structure coupled to the nozzle. The generator outputs groups of droplets. A control system applies a voltage waveform to the piezoelectric structure while the nozzle outputs the group of droplets. The waveform causes the droplets of the group to have a spread of velocities that results in the droplets coalescing into a single droplet prior to being irradiated by the laser.

Abstract: An embodiment of the present disclosure provides a semiconductor device arrangement. This arrangement includes a substrate, an adhesive structure, and a first semiconductor device. The substrate includes an upper surface. The adhesive structure is located on the upper surface and includes a first concave region. The first semiconductor device includes a lower surface facing toward the adhesive structure and a conductive bump located under the lower surface and in the first concave region. The conductive bump includes a first portion and a second portion. Wherein the lower surface does not contact the adhesive structure, the first portion contacts the first concave region, and the second portion does not contact the first concave region.

Abstract: Methods of singulation and bonding, as well as structures formed thereby, are disclosed. A method includes singulating a first chip and after the singulating the first chip, bonding the first chip to a second chip. The first chip includes a first semiconductor substrate and a first interconnect structure on a front side of the first semiconductor substrate. The singulating the first chip includes etching through a back side of the first semiconductor substrate through the first interconnect structure.

Abstract: A semiconductor package includes an interconnect structure including a redistribution structure, an insulating layer over the redistribution structure, and conductive pillars on the insulating layer, wherein the conductive pillars are connected to the redistribution structure, wherein the interconnect structure is free of active devices, a routing substrate including a routing layer over a core substrate, wherein the interconnect structure is bonded to the routing substrate by solder joints, wherein each of the solder joints bonds a conductive pillar of the conductive pillars to the routing layer, an underfill surrounding the conductive pillars and the solder joints, and a semiconductor device including a semiconductor die connected to a routing structure, wherein the routing structure is bonded to an opposite side of the interconnect structure as the routing substrate.

Abstract: A fuel tank cap includes a seal cap body and a detaching-proof unit. The cap body has a handheld wall and a surrounding wall that extends from the handheld wall and that is formed with an engaging groove. The detaching-proof unit includes a ring sleeve member and a connection member. The ring sleeve member has an outer ring wall that surrounds the surrounding wall, and a resilient wall that extends the outer ring wall and that is engaged resiliently with the engaging groove. The connection member is connected to the ring sleeve member to be connected to a cap installation portion of a vehicle body.

Abstract: Methods of singulation and bonding, as well as structures formed thereby, are disclosed. A method includes singulating a first chip and after the singulating the first chip, bonding the first chip to a second chip. The first chip includes a first semiconductor substrate and a first interconnect structure on a front side of the first semiconductor substrate. The singulating the first chip includes etching through a back side of the first semiconductor substrate through the first interconnect structure.

Abstract: A biochip includes a chip unit and an elastic pad. The chip unit comprises a plurality of liquid inlets arranged at intervals, and a plurality of micro flow channels respectively communicating with the liquid inlets. The elastic pad has an upper surface and a lower surface, and the lower surface is pasted on the chip unit. The elastic pad includes a plurality of guide channels arranged at intervals and penetrating the upper surface and the lower surface of the elastic pad. The guide channels respectively correspond to the liquid inlets of the chip unit. Each guide channel has an upper guiding section, and the diameter of the upper guiding section is gradually reduced from top to bottom. The detection liquid can enter the chip unit more quickly through the guide channel and improving the detection efficiency and accuracy. The invention also provides a connector module used in conjunction with the biochip.

Abstract: A semiconductor package and methods of forming the same are disclosed. In an embodiment, a package includes a substrate; a first die disposed within the substrate; a redistribution structure over the substrate and the first die; and an encapsulated device over the redistribution structure, the redistribution structure coupling the first die to the encapsulated device.

Abstract: A display panel including a substrate, a light emitting structure layer, a C-plate, and a first bandpass polarizing reflective layer is provided. The light emitting structure layer is disposed on the substrate and includes first light emitting structures. The first light emitting structures have a first peak emission wavelength. The C-plate is disposed on a side of the light emitting structure layer away from the substrate. The first bandpass polarizing reflective layer is disposed between the light emitting structure layer and the C-plate and overlapped with the light emitting structure layer. A reflectance of the first bandpass polarizing reflective layer for light with a wavelength in a first wavelength range is greater than 20%. The first wavelength range is the first peak emission wavelength±20 nm.

Abstract: A semiconductor device and method of manufacture is provided including a redistribution structure; a plurality of core substrates attached to the redistribution structure using conductive connectors, each core substrate of the plurality of core substrates comprising a plurality of conductive posts; and one or more molding layers encapsulating the plurality of core substrates, where the one or more molding layers extends along sidewalls of the plurality of core substrates, and where the one or more molding layers extends along a portion of a sidewall of each of the conductive posts.

Abstract: An integrated circuit package that includes symmetrical redistribution structures on either side of a core substrate is provided. In an embodiment, a device comprises a core substrate, a first redistribution structure comprising one or more layers, a second redistribution comprising one or more layers, a first integrated circuit die, and a set of external conductive features. The core substrate is disposed between the first redistribution structure and the second redistribution structure, the first integrated circuit die is disposed on the first distribution structure on the opposite side from the core substrate; and the set of external conductive features are disposed on a side of the second redistribution structure opposite the core substrate. The first redistribution structure and second redistribution structure have symmetrical redistribution layers to each other with respect to the core substrate.

Abstract: The application provides a wireless communication method and a wireless communication device. A part of payload is pre-fetched from a host to a data buffer under a store-and-forward mode before transmission begins. When data transmission begins, the part of the payload pre-fetched in the data buffer is transmitted to an antenna. A remaining part of the payload is fetched to the data buffer under a cut-through mode for payload transmission, wherein the remaining part of the payload is sent from the data buffer to the antenna for radiation.

Abstract: A joint orthosis assembly includes a web, an arm unit, a strap unit, and at least one fastening subassembly. The web has three web portions for being wrapped on an upper limb structure, a lower limb structure, and a joint between the upper and lower limb structures, respectively. The arm unit is retained on the web and includes two arms which are pivotally connected, and which are for being disposed at lateral sides of the upper and lower limb structures, respectively. The strap unit includes two straps each being wound about the web to be coupled between the two arms. The fastening subassembly is configured to permit an end of at least one of the straps to be turnably coupled to a corresponding one of arms.

Abstract: The present disclosure provides a fast charging driver. The fast charging driver is configured to charge a battery of an electronic device. The fast charging driver includes a fast charging circuit and a charging controller. The fast charging circuit includes a first depletion-type GaN transistor, a first enhancement-type field effect transistor, a second depletion-type GaN transistor and a second enhancement-type field effect transistor. The charging controller is configured to control the fast charging circuit to operate in a constant current mode or a constant voltage mode according to a battery level of the battery. By utilizing the first depletion-type GaN transistor and the second depletion-type GaN transistor with a characteristic of a relatively low switching loss, the power consumption during charging the battery by the fast charging driver is decreased to improve the charge speed.

Abstract: A semiconductor package includes an interconnect structure including a redistribution structure, an insulating layer over the redistribution structure, and conductive pillars on the insulating layer, wherein the conductive pillars are connected to the redistribution structure, wherein the interconnect structure is free of active devices, a routing substrate including a routing layer over a core substrate, wherein the interconnect structure is bonded to the routing substrate by solder joints, wherein each of the solder joints bonds a conductive pillar of the conductive pillars to the routing layer, an underfill surrounding the conductive pillars and the solder joints, and a semiconductor device including a semiconductor die connected to a routing structure, wherein the routing structure is bonded to an opposite side of the interconnect structure as the routing substrate.