Patents by Inventor Hua Yang

Hua Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240126533
    Abstract: A computing device and methods for deploying a software update to the computing device are provided. The method for deploying the software update by a high-level operating system (HLOS) processor includes receiving, by the HLOS processor, the software update request; updating a code package of the HLOS processor; and transmitting, by the code package, a software update to a shared file system, where the shared file system is shared between the HLOS processor and a software stack of a modem processor, and the software update is configured to cause the modem processor to deploy the software update to the software stack of the modem processor in an instance in which a file change is detected in the shared file system.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 18, 2024
    Inventors: Shanning YANG, Hua ZHANG, Shangfei TANG, Yaqing LU
  • Publication number: 20240122875
    Abstract: Provided is a use of a mitoxantrone hydrochloride liposome in the preparation of a drug for treating urothelial cancer, breast cancer, and bone and soft tissue sarcoma. Further provided is a method for treating urothelial cancer, breast cancer, and bone and soft tissue sarcoma, and the method is to administer a therapeutically effective amount of mitoxantrone hydrochloride liposomes to a patient in need. The mitoxantrone hydrochloride liposome can effectively treat urothelial cancer, breast cancer, and bone and soft tissue sarcoma, and compared with common mitoxantrone hydrochloride injections, the mitoxantrone hydrochloride liposome has better therapeutic effect and fewer adverse reactions.
    Type: Application
    Filed: April 15, 2022
    Publication date: April 18, 2024
    Applicant: CSPC ZHONGQI PHARMACEUTICAL TECHNOLOGY (SHIJIAZHUANG) CO., LTD
    Inventors: Chunlei LI, Yanping LIU, Min LIANG, Mengmeng LI, Tong LI, Hua YANG, Shixia WANG, Sensen YANG
  • Publication number: 20240125712
    Abstract: The present invention relates to a macro plastic and micro plastic detection method based on RGB and hyperspectral image fusion, which includes the following steps: obtaining macro plastics and micro plastics; mixing with solid wastes to obtain a solid-phase substrate; pretreating the obtained solid-phase substrate to obtain a material; drying to remove part of moisture and coating on a quartz window sheet, drying until the moisture is completely removed, and flattening by using another quartz window sheet to obtain a material to be detected; obtaining an RGB image and a hyperspectral image of the material to be detected respectively by using a high-resolution color image scanner and a hyperspectral camera; fusing the obtained RGB image and hyperspectral image; and automatically classifying and identifying the macro plastics and the micro plastics by using a supervised classification model.
    Type: Application
    Filed: December 5, 2023
    Publication date: April 18, 2024
    Applicant: TONGJI UNIVERSITY
    Inventors: Pinjing He, Zhan YANG, Hua Zhang, Fan Lyu, Wei PENG
  • Patent number: 11958789
    Abstract: A method for determining a consistency coefficient of a power-law cement grout includes: determining a water-cement ratio of the power-law cement grout; according to engineering practice requirements, determining a time required to determine the consistency coefficient of the power-law cement grout; and obtaining the consistency coefficient of the power-law cement grout. The method is accurate and reliable, requires less calculation, etc.; and has very high practical value and popularization value in environmental protection and ecological restoration.
    Type: Grant
    Filed: December 12, 2023
    Date of Patent: April 16, 2024
    Assignee: KUNMING UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Zhi-quan Yang, Jun-fan Xiong, Ying-yan Zhu, Yi Yang, Yong-shun Han, Muhammad Asif Khan, Jian-bin Xie, Tian-bing Xiang, Bi-hua Zhang, Han-hua Xu, Jie Zhang, Shen-zhang Liu, Qi-jun Jia, Cheng-yin Ye, Gang Li
  • Patent number: 11959962
    Abstract: Apparatus and techniques for an integrated circuit (IC) package to automatically detect, through an input/out pin, external component parameters and parasitics. An example IC package generally includes a pin for coupling to a component external to the IC package, and at least one of a resistance detector, an inductance detector, or a capacitance detector coupled to the pin, and configured to detect at least one of a resistance, an inductance, or a capacitance, respectively, of a lumped parameter model for the component external to the IC package. The resistance detector, inductance detector, or capacitance detector may also be configured to detect parasitics associated with at least one of the component, the pin, or a connection between the component and the pin.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: April 16, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Chengyue Yu, Hua Guan, Yingjie Chen, Fan Yang, Yufei Pan, Jize Jiang, Shamim Ahmed
  • Publication number: 20240118150
    Abstract: The present disclosure provides a method for testing an internal force increment of an arch bridge suspender by inertial measurement, including the following steps: (1) selecting a suspender to be tested with internal force increment, and mounting an acceleration sensing device or a speed sensing device at a lower edge of the suspender to be tested; (2) setting an appropriate sampling frequency and collecting signals; (3) processing information data collected in step (2) by using Formulas; and (4) recording a result of the information data processing and obtaining the internal force increment of the suspender. The method can obtain the internal force increment of the suspender by collecting acceleration or speed signals of the lower edge of the suspender and performing calculation from the signals. This method has the advantages of simple and convenient testing, high replicability and low test cost.
    Type: Application
    Filed: October 8, 2021
    Publication date: April 11, 2024
    Inventors: Hua Wang, Longlin Wang, Tianzhi Hao, Zehua Xie, Mengsheng Yu, Xiaoli Zhuo, Yuhou Yang, Jiejun Ning, Xirui Wang, Xi Peng, Kainan Huang, Junhong Wu
  • Patent number: 11953728
    Abstract: A method of transfer printing. The method comprising: providing a precursor photonic device, comprising a substrate and a bonding region, wherein the precursor photonic device includes one or more alignment marks located in or adjacent to the bonding region; providing a transfer die, said transfer die including one or more alignment marks; aligning the one or more alignment marks of the precursor photonic device with the one or more alignment marks of the transfer die; and bonding at least a part of the transfer die to the bonding region.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: April 9, 2024
    Assignee: Rockley Photonics Limited
    Inventors: Guomin Yu, Mohamad Dernaika, Ludovic Caro, Hua Yang, Aaron John Zilkie
  • Patent number: 11955378
    Abstract: A bonding method of package components and a bonding apparatus are provided. The method includes: providing at least one first package component and a second package component, wherein the at least one first package component has first electrical connectors and a first dielectric layer at a bonding surface of the at least one first package component, and the second package component has second electrical connectors and a second dielectric layer at a bonding surface of the second package component; bringing the at least one first package component and the second package component in contact, such that the first electrical connectors approximate or contact the second electrical connectors; and selectively heating the first electrical connectors and the second electrical connectors by electromagnetic induction, in order to bond the first electrical connectors with the second electrical connectors.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Li Hsiao, Chih-Hang Tung, Chen-Hua Yu, Tung-Liang Shao, Su-Chun Yang
  • Publication number: 20240114116
    Abstract: A multi-projector system and a method of calibrating the multi-projector system are provided. The method includes: controlling a first projector to project a first image, and capturing and generating a first captured image including the first image to obtain a first color value from the first captured image through an image capturing device; projecting a second image according to a first projection parameter, and capturing and generating a second captured image including the second image to obtain a second color value from the second captured image through the image capturing device, wherein the first projection parameter includes an electrical parameter of a light source module of the second projector; calculating an absolute difference between the first color value and the second color value; and adjusting the first projection parameter to update the absolute difference in response to the absolute difference being greater than a first threshold.
    Type: Application
    Filed: September 25, 2023
    Publication date: April 4, 2024
    Applicant: Coretronic Corporation
    Inventors: Xuan-En Fung, Chun-Lin Chien, Yu-Wen Lo, Yu-Hua Yang
  • Patent number: 11946845
    Abstract: A method for determining a three-dimensional tortuosity of a loose and broken rock-soil mass, includes the following steps: a particle grading curve of the loose and broken rock-soil mass is obtained by utilizing a particle size analysis, and followed by calculating an equivalent particle size and an average particle size; a porosity of the loose and broken rock-soil mass is obtained by utilizing a moisture content test, a density test, and a specific gravity test; the three-dimensional tortuosity of the loose and broken rock-soil mass is obtained by utilizing the equivalent particle size, the average particle size and the porosity of the loose and broken rock-soil mass. The method has the advantages of simple logic, accuracy and reliability, simple and fast parameter determination, and has high practical value and promotion value in the field of environmental protection and ecological restoration technology.
    Type: Grant
    Filed: November 1, 2023
    Date of Patent: April 2, 2024
    Assignee: KUNMING UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Zhi-quan Yang, Jia-jun Zhang, Jun-fan Xiong, Ying-yan Zhu, Yi Yang, Muhammad Asif Khan, Tian-bing Xiang, Bi-hua Zhang, Han-hua Xu, Jie Zhang, Shen-zhang Liu
  • Patent number: 11948971
    Abstract: A method includes forming isolations extending into a semiconductor substrate, recessing the isolation regions, wherein a semiconductor region between the isolation regions forms a semiconductor fin, forming a first dielectric layer on the isolation regions and the semiconductor fin, forming a second dielectric layer over the first dielectric layer, planarizing the second dielectric layer and the first dielectric layer, and recessing the first dielectric layer. A portion of the second dielectric layer protrudes higher than remaining portions of the first dielectric layer to form a protruding dielectric fin. A portion of the semiconductor fin protrudes higher than the remaining portions of the first dielectric layer to form a protruding semiconductor fin. A portion of the protruding semiconductor fin is recessed to form a recess, from which an epitaxy semiconductor region is grown. The epitaxy semiconductor region expands laterally to contact a sidewall of the protruding dielectric fin.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Wei Yu, Tsz-Mei Kwok, Tsung-Hsi Yang, Li-Wei Chou, Ming-Hua Yu
  • Patent number: 11950424
    Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a first gate electrode disposed on the substrate and located in a first region of the semiconductor device. The semiconductor device also includes a first sidewall structure covering the first gate electrode. The semiconductor device further includes a protective layer disposed between the first gate electrode and the first sidewall structure. In addition, the semiconductor device includes a second gate electrode disposed on the substrate and located in a second region of the semiconductor device. The semiconductor device also includes a second sidewall structure covering a lateral surface of the second gate electrode.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Ting Tsai, Ching-Tzer Weng, Tsung-Hua Yang, Kao-Chao Lin, Chi-Wei Ho, Chia-Ta Hsieh
  • Publication number: 20240105851
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first well region and a second well region in a substrate. The method includes forming a third well region in the substrate and between the first well region and the second well region. The method includes forming a deep well region in the substrate and under the first well region and the third well region. The method includes partially removing the substrate to form a first fin, a second fin, and a third fin in the first well region, the second well region, and the third well region respectively. The method includes forming a first epitaxial structure, a second epitaxial structure, and a third epitaxial structure in the first recess, the second recess, and the third recess respectively.
    Type: Application
    Filed: January 12, 2023
    Publication date: March 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiefeng Jeff LIN, Chen-Hua TSAI, Shyh-Horng YANG
  • Publication number: 20240102129
    Abstract: A nonlinear oxygen-enriched injection method based on chaotic mapping and electronic device is disclosed, including: obtaining a chaotic gas injection volume corresponding to a current speed change period according to a chaotic mapping value corresponding to the current speed change period and a peak gas injection volume in an oxygen-enriched injection process; determining a rotational speed of a fan blade in a fan component corresponding to the current speed change period according to the chaotic gas injection volume; updating a rotational speed of a direct current (DC) motor in the fan component corresponding to the current speed change period according to the rotational speed of the fan blade in the fan component, and driving the fan blade to rotate according to an updated rotational speed of the DC motor, so as to update an air output of the fan component. The above operations are repeated until a last stage.
    Type: Application
    Filed: February 3, 2023
    Publication date: March 28, 2024
    Inventors: Hua WANG, Kai YANG, Qingtai XIAO
  • Publication number: 20240105549
    Abstract: The systems and cold plate pedestal and assembly described decrease mechanical stresses in integrated circuits, while also providing efficient thermal coupling between heat producing components and a cold plate. A cold plate assembly includes a cold plate with a pedestal portion a groove formed in a surface of the pedestal portion. The cold plate assembly also includes a thermal pad layer formed in the groove and a phase change material (PCM) layer formed on the surface of the pedestal portion and a surface of the thermal pad layer formed in the groove.
    Type: Application
    Filed: February 15, 2023
    Publication date: March 28, 2024
    Inventors: Yongguo CHEN, Kai CAO, Hua YANG, Vic Hong CHIA, Paul TON
  • Publication number: 20240092851
    Abstract: The disclosure provides IL-7 fusion proteins as well as compositions comprising them. The disclosure further provides methods of treating and/or preventing lymphopenia or immunodeficiency in a subject, wherein the method includes administering a fusion protein as described herein.
    Type: Application
    Filed: November 23, 2021
    Publication date: March 21, 2024
    Inventors: Shusheng Wang, Jianwei Zhu, Haiqiu Huang, Ailin Wang, Kaiyong Yang, Yueqing Xie, Hua Jiang
  • Publication number: 20240097258
    Abstract: A battery box and a battery pack are provided. The battery box includes a bottom plate and a side wall. The side wall and the bottom plate enclose a space for accommodating a battery and/or an electrical component. The battery box further includes a lifting column integrally formed with the side wall and a fixed sealing block sleeved on the lifting column. The bottom plate is located between the side wall and the fixed sealing block. The side wall is fixedly connected to the bottom plate through the fixed sealing block. A first sealing member for sealing a gap between the fixed sealing block and the bottom plate is arranged between the fixed sealing block and the bottom plate. The fixed sealing block is sealingly connected to the lifting column.
    Type: Application
    Filed: March 7, 2023
    Publication date: March 21, 2024
    Applicant: CALB Group Co., Ltd.
    Inventors: Zhaoyang Jin, Shuaifeng Wang, Xulong Yang, Hua Chen, Xinwei Jiang
  • Publication number: 20240096847
    Abstract: A method includes putting a first package component into contact with a second package component. The first package component comprises a first dielectric layer including a first dielectric material, and the first dielectric material is a silicon-oxide-based dielectric material. The second package component includes a second dielectric layer including a second dielectric material different from the first dielectric material. The second dielectric material comprises silicon and an element selected from the group consisting of carbon, nitrogen, and combinations thereof. An annealing process is performed to bond the first dielectric layer to the second dielectric layer.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Ku-Feng Yang, Ming-Tsu Chung
  • Publication number: 20240088124
    Abstract: A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 14, 2024
    Inventors: HSIANG-TAI LU, SHUO-MAO CHEN, MILL-JER WANG, FENG-CHENG HSU, CHAO-HSIANG YANG, SHIN-PUU JENG, CHENG-YI HONG, CHIH-HSIEN LIN, DAI-JANG CHEN, CHEN-HUA LIN
  • Publication number: 20240088061
    Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Shu-Shen Yeh, Che-Chia Yang, Chin-Hua Wang, Po-Yao Lin, Shin-Puu Jeng, Chia-Hsiang Lin