Abstract: One embodiment of a method for constructing executable code for a component-based application includes receiving a request to compile source code for the component-based application, wherein the request identifies the source code, and wherein the source code comprises a plurality of source code components, each of the source code components implementing a different component of the application, and performing a series of steps for each source code component where the series of steps includes: deriving a signature for the source code component, retrieving a stored signature corresponding to a currently available instance of executable code for the source code component, comparing the derived signature with the stored signature, compiling the source code component into the executable code when the derived signature does not match the stored signature, and obtaining the executable code for the source code component from a repository when the derived signature matches the stored signature.

Abstract: A step motor driving apparatus includes a micro control unit (MCU), a pulse generator, a first step motor driver, a second step motor driver, and a communication port. The first step motor driver is configured for driving a first step motor and connected to the MCU. The second step motor driver is configured for driving a second step motor and connected to the MCU. The MCU is connected to the second step motor driver via the pulse generator. The pulse generator is configured to supply pulse signals to the second step motor driver. The communication port is connected to the MCU. The MCU receives a corresponding command from an external control apparatus via the communication port. The MCU selectively controls the first step motor driver to drive the first step motor or controls the second step motor driver to drive the second step motor according to the command.

Abstract: This invention provides a system enabling Transactional Memory with overflow prediction mechanism, comprising: prediction unit for predicting the mode for the next execution of a transaction based on the final status of the previous execution of the transaction; execution unit for executing the transaction in the execution mode predicted by the prediction unit, wherein the execution mode comprises overflow mode and non-overflow made. According to this invention, before a transaction is executed, it is predicted whether or not the transaction will overflow, and therefore, the execution of the transaction which is necessary to determine whether or not an overflow will occur is saved and the system performance can be improved.

Abstract: There are disclosed a method and device for performing Copy-on-Write in a processor. The processor comprises: processor cores, L1 caches each of which is logically divided into a first L1 cache and a second L1 cache, and L2 caches. The first L1 cache is used for saving new data value, and the second L1 cache for saving old data value. The method can comprise the steps of: in response to a store operation from said processor core, judging whether a corresponding cache line in said L2 cache has been modified; if it is determined a corresponding L2 cache line in said L2 cache has not been modified, copying old data value in the corresponding L2 cache line to said second L1 cache, and writing new data value to the corresponding L2 cache line; and if it is determined a corresponding L2 cache line in said L2 cache has been modified, writing new data value to the corresponding L2 cache line directly.

Abstract: There is disclosed a method and apparatus for handling transaction buffer overflow in a multi-processor system as well as a transaction memory system in a multi-processor system. The method comprises the steps of: when overflow occurs in a transaction buffer of one processor, disabling peer processors from entering transactions, and waiting for any processor having a current transaction to complete its current transaction; re-executing the transaction resulting in the transaction buffer overflow without using the transaction buffer; and when the transaction execution is completed, enabling the peer processors for entering transactions.

Abstract: A method and apparatus for implementing transactional memory (TM). The method includes: allocating a hardware-based transaction footprint recorder to the transaction, for recording footprints of the transaction when a transaction is begun; determining that the transaction is to be switched out; and switching out the transaction, where the footprints of the switched-out transaction are still kept in the hardware-based transaction footprint recorder. According to the present invention, transaction switching is supported by TM, and the cost of conflict detection between an active transaction and a switched-out transaction is greatly reduced since the footprints of the switched-out transaction are still kept in the hardware-based transaction footprint recorder.

Abstract: A method, apparatus, and full-system simulator for speeding memory management unit simulation with direct address mapping on a host system, the host system supporting a full-system simulator, on which a guest system is simulated, the method comprising the following steps: setting a border in the logical space assigned for the full-system simulator by the host system, thereby dividing the logical space into a safe region and a simulator occupying region; shifting the full-system simulator itself from the occupied original host logical space to the simulator occupying region; and reserving the safe region for use with at least part of the guest system.

Abstract: A step motor driving apparatus includes a micro control unit (MCU), a pulse generator, a first step motor driver, a second step motor driver, and a communication port. The first step motor driver is configured for driving a first step motor and connected to the MCU. The second step motor driver is configured for driving a second step motor and connected to the MCU. The MCU is connected to the second step motor driver via the pulse generator. The pulse generator is configured to supply pulse signals to the second step motor driver. The communication port is connected to the MCU. The MCU receives a corresponding command from an external control apparatus via the communication port. The MCU selectively controls the first step motor driver to drive the first step motor or controls the second step motor driver to drive the second step motor according to the command.

Abstract: Methods and systems are provided for analyzing parallelism of program code. According to a method, the sequential execution of the program code is simulated so as to trace the execution procedure of the program code, and parallelism of the program code is analyzed based on the result of the trace to the execution procedure of the program code. Execution information of the program code is collected by simulating the sequential execution of the program code, and parallelism of the program code is analyzed based on the collected execution information, so as to allow programmers to perform parallel task partitioning of the program code with respect to a multi-core architecture more effectively, thus increasing the efficiency of parallel software development.

Abstract: Disclosed is a method of recognizing a process in a full-system Industry Standard Architecture (ISA) emulator, comprising the steps of: recognizing a process based on a base address of a page table thereof, recognizing the switch between the processes when said base address of the page table has changed, recognizing the termination of a recorded process when the base address of the page table of the process which tries to modify the page table is not equal to the base address of the page table of the recorded process in the page table. With the recognized process, the binary translation results indexed based on content can be saved into a corresponding process repository, thereby achieving the permanent saving of the translation results and the reuse of translation and optimization on the basis of a previously executed program. Consequently, the overall performance of the full-system Industry Standard Architecture emulator is enhanced.

Abstract: A method for performing rapid memory management unit emulation of a computer program in a computer system, wherein address injection space of predefined size is allocated in the computer system and a virtual page number and a corresponding physical page number are stored in said address injection space, said method comprising steps of: comparing the virtual page number of the virtual address of a load/store instruction in a code segment in said computer program with the virtual address page number stored in said address injection space; if the two virtual page numbers are the same, then obtaining the corresponding physical address according to the physical page number stored in said address injection space; otherwise, performing address translation lookaside buffer search, that is, TLB search to obtain the corresponding physical address; and reading/writing data from/to said obtained corresponding physical address.