Abstract: Method for forming semiconductor device structure includes forming a sacrificial layer between first and second stacks of layers, the first stack of layers comprises first and second semiconductor layers alternatingly stacked, and the second stack of layers comprises third and fourth semiconductor layers alternatingly stacked, wherein the sacrificial layer comprises a semiconductor metal oxide, forming a sacrificial gate structure over portion of the second stack of layers, removing portions of the first and second stack of layers not covered by the sacrificial gate structure, removing the sacrificial layer to form cavity, filling the cavity with a dielectric to form an isolation layer, and forming first and second source/drain features on opposing sides of sacrificial gate structure, wherein the first source/drain feature is disposed below the second source/drain feature, and the first and second source/drain features are in contact with the isolation layer, first semiconductor layers, and third semiconducto

Abstract: The disclosure generally relates to systems, methods, and apparatuses for magnetic bead loading. An example embodiment of the disclosure relates to an apparatus including a vertically oriented plate having a first major surface and a second major surface opposite the first major surface; a magnet holder securing a magnet in proximity to the first major surface of the vertically oriented plate; a drive mechanism coupled to the magnet holder and operable to move the magnet holder and magnet in parallel to the first major surface of the vertically oriented plate; and a substrate holder to receive a substrate and hold the substrate in a vertical orientation against the surface of the vertically oriented plate.

Abstract: A photonic assembly includes: an electronic integrated circuits (EIC) die including a semiconductor substrate, semiconductor devices located on a horizontal surface of the semiconductor substrate, first dielectric material layers embedding first metal interconnect structures, a dielectric pillar structure vertically extending through each layer selected from the first dielectric material layers, a first bonding-level dielectric layer embedding first metal bonding pads, wherein a first subset of the first metal bonding pads has an areal overlap with the dielectric pillar structure in a plan view; and a photonic integrated circuits (PIC) die including waveguides, photonic devices, second dielectric material layers embedding second metal interconnect structures, a second bonding-level dielectric layer embedding second metal bonding pads, wherein the second metal bonding pads are bonded to the first metal bonding pads.

Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

Abstract: In an embodiment, a package includes a first package structure including a first die having a first active side and a first back-side, the first active side including a first bond pad and a first insulating layer a second die bonded to the first die, the second die having a second active side and a second back-side, the second active side including a second bond pad and a second insulating layer, the second active side of the second die facing the first active side of the first die, the second insulating layer being bonded to the first insulating layer through dielectric-to-dielectric bonds, and a conductive bonding material bonded to the first bond pad and the second bond pad, the conductive bonding material having a reflow temperature lower than reflow temperatures of the first and second bond pads.

Abstract: An electro-optical device includes a waveguide and a first electrode and a second electrode. The first electrode and the second electrode at first and second sides of the waveguide, wherein the first electrode and the second electrode directly contact and extend beyond the first and second sides of the waveguide respectively.

Abstract: Systems, devices and methods of manufacturing a system on silicon wafer (SoSW) device and package are described herein. A plurality of functional dies is formed in a silicon wafer. Different sets of masks are used to form different types of the functional dies in the silicon wafer. A first redistribution structure is formed over the silicon wafer and provides local interconnects between adjacent dies of the same type and/or of different types. A second redistribution structure may be formed over the first redistribution layer and provides semi-global and/or global interconnects between non-adjacent dies of the same type and/or of different types. An optional backside redistribution structure may be formed over a second side of the silicon wafer opposite the first redistribution layer. The optional backside redistribution structure may provide backside interconnects between functional dies of different types.

Abstract: A semiconductor device includes: a photodiode including a germanium material portion laterally extending along a first horizontal direction, a p-doped silicon portion, and an n-doped silicon portion; and a distributed Bragg reflector including multiple periodic repetitions of a unit layer stack including a first material layer and a second material layer, wherein interfaces between vertically-extending portions of material layers within the distributed Bragg reflector are perpendicular to the first horizontal direction, and wherein the distributed Bragg reflector is in contact with the germanium material portion.

Abstract: A method includes forming a first passivation layer, forming a metal pad over the first passivation layer, forming a planarization layer having a planar top surface over the metal pad, and patterning the planarization layer to form a first opening. A top surface of the metal pad is revealed through the first opening. The method further includes forming a polymer layer extending into the first opening, and patterning the polymer layer to form a second opening. The top surface of the metal pad is revealed through the second opening.

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a front side of a wafer, the wafer having a plurality of dies at the front side of the wafer, the first dielectric layer having a first shrinkage ratio smaller than a first pre-determined threshold; curing the first dielectric layer at a first temperature, where after curing the first dielectric layer, a first distance between a highest point of an upper surface of the first dielectric layer and a lowest point of the upper surface of the first dielectric layer is smaller than a second pre-determined threshold; thinning the wafer from a backside of the wafer; and performing a dicing process to separate the plurality of dies into individual dies.

Abstract: A method of fabrication a package and a stencil structure are provided. The stencil structure includes a first carrier having a groove and stencil units placed in the groove of the first carrier. At least one of the stencil units is slidably disposed along sidewalls of another stencil unit. Each of the stencil units has openings.

Abstract: Optical devices and methods of manufacture are presented in which glass interposers are incorporated with optical devices. In some embodiments a method includes forming a first optical package and then bonding the first optical package to a first glass interposer. The first glass interposer may then be connected to a second interposer.

Abstract: Provided herein are compositions and methods for the multiplexed profiling of RNA and DNA modifications across transcriptomes and genomes, respectively. The methods combine molecular recognition of non-canonical features (e.g., base modifications, backbone modifications, lesions, and/or structural elements) of a target nucleic acid with a step of writing the information from this recognition event into the neighboring genetic sequence of the target nucleic acid using a barcode. The resultant barcoded nucleic acids are then converted into sequencing libraries and read by DNA/RNA sequencing methods. This step reveals the sequence of the barcode, which is correlated with the non-canonical feature in the target nucleic acid(s). The high throughput profiling methods described herein allow for identification and/or localization of one or more modifications in a target nucleic acid. The methods also allow for identification of the nature and location of several or all DNA/RNA modifications in parallel.

Abstract: A method includes placing an electronic die and a photonic die over a carrier, with a back surface of the electronic die and a front surface of the photonic die facing the carrier. The method further includes encapsulating the electronic die and the photonic die in an encapsulant, planarizing the encapsulant until an electrical connector of the electronic die and a conductive feature of the photonic die are revealed, and forming redistribution lines over the encapsulant. The redistribution lines electrically connect the electronic die to the photonic die. An optical coupler is attached to the photonic die. An optical fiber attached to the optical coupler is configured to optically couple to the photonic die.

Abstract: A package structure is provided. The package structure includes a die, an encapsulant and a RDL structure. The RDL structure is disposed on the die and the encapsulant. The RDL structure includes a first dielectric structure and a first redistribution layer. The first dielectric structure includes a first dielectric material layer and a second dielectric material layer on the first dielectric material layer. The first redistribution layer is embedded in the first dielectric structure and electrically connected to the die. The redistribution layer includes a first seed layer and a first conductive layer surrounded by the first seed layer. A topmost surface of the first seed layer and a topmost surface of the first conductive layer are substantially level with a top surface of the second dielectric material layer.

Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.

Abstract: A method of manufacturing a semiconductor package includes the following steps. A first redistribution layer structure is formed over a circuit board structure. A through via is formed over the first redistribution layer structure. A first die is mounted onto the first redistribution layer structure aside the through via. A first encapsulant is formed to encapsulate the first die and the through via, wherein surfaces of the first encapsulant, the first die and the through via are substantially coplanar.

Abstract: The present disclosure describes a semiconductor device having a source/drain structure with a dopant cluster. The semiconductor device includes a channel structure on a substrate and a source/drain structure on the substrate and adjacent to the channel structure. The source/drain structure includes a first epitaxial layer on the substrate, a second epitaxial layer on the first epitaxial layer and sidewalls of the channel structure, and a third epitaxial layer on the second epitaxial layer. The second epitaxial layer includes a cluster of a dopant extending along a direction of the channel structure.

Abstract: A package includes an interposer, wherein the interposer includes a first waveguide and a first reflector that is optically coupled to the first waveguide; an optical package attached to the interposer, wherein the optical package includes a second waveguide; and a second reflector that is optically coupled to the second waveguide, wherein the second reflector is vertically aligned with the first reflector.

Abstract: Circuit board includes conductive plate, core dielectric layer, metallization layer, first build-up stack, second build-up stack. Conductive plate has channels extending from top surface to bottom surface. Core dielectric layer extends on covering top surface and side surfaces of conductive plate. Metallization layer extends on core dielectric layer and within channels of conductive plate. Core dielectric layer insulates metallization layer from conductive plate. First build-up stack is disposed on top surface of conductive plate and includes conductive layers alternately stacked with dielectric layers. Conductive layers electrically connect to metallization layer. Second build-up stack is disposed on bottom surface of conductive plate. Second build-up stack includes bottommost dielectric layer and bottommost conductive layer. Bottommost dielectric layer covers bottom surface of conductive plate.