Patents by Inventor Hua Yu

Hua Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12230513
    Abstract: A method includes placing a plurality of package components over a carrier, encapsulating the plurality of package components in an encapsulant, forming a light-sensitive dielectric layer over the plurality of package components and the encapsulant, exposing the light-sensitive dielectric layer using a lithography mask, and developing the light-sensitive dielectric layer to form a plurality of openings. Conductive features of the plurality of package components are exposed through the plurality of openings. The method further includes forming redistribution lines extending into the openings. One of the redistribution lines has a length greater than about 26 mm. The redistribution lines, the plurality of package components, the encapsulant in combination form a reconstructed wafer.
    Type: Grant
    Filed: January 11, 2024
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Chen-Hua Yu, Tin-Hao Kuo
  • Patent number: 12228776
    Abstract: A method includes forming a package, which includes an optical die and a protection layer attached to the optical die. The optical die includes a micro lens, with the protection layer and the micro lens being on a same side of the optical die. The method further includes encapsulating the package in an encapsulant, planarizing the encapsulant to reveal the protection layer, and removing the protection layer to form a recess in the encapsulant. The optical die is underlying the recess, with the micro lens facing the recess.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hua Yu, Jiun Yi Wu
  • Patent number: 12226745
    Abstract: The present disclosure provides methods, compositions and kits as well as systems for manipulating nucleic acids, including implementing isothermal amplification, such as recombinase-polymerase amplification (RPA), of a nucleic acid template using a pre-seeded solid support. Provided are rapid and efficient methods for generating template nucleic acid molecules comprising specific nucleotide sequence bound to solid support. Such methods can be used, for example, in manipulating nucleic acids in preparation for analysis methods that utilize monoclonal populations of nucleic acids.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: February 18, 2025
    Assignee: Life Technologies Corporation
    Inventors: Abraham Rosenbaum, Collyn Seeger, Jeremy Gray, Hua Yu
  • Publication number: 20250052963
    Abstract: A method for forming an optical device structure is provided. The method includes disposing a first end portion of an optical fiber into a fiber array unit structure. The first end portion penetrates through the fiber array unit structure. The method includes bonding the first end portion of the optical fiber to a co-packaged optical device. The method includes bonding a fiber shield structure to the fiber array unit structure and the co-packaged optical device after the first end portion is bonded to the co-packaged optical device. The fiber shield structure surrounds the optical fiber.
    Type: Application
    Filed: August 7, 2023
    Publication date: February 13, 2025
    Inventors: Chien-Yuan HUANG, Shih-Chang KU, Chen-Hua YU, Chuei-Tang WANG
  • Publication number: 20250053064
    Abstract: Optical devices and methods of manufacture are presented in which a non-linear material is deposited or otherwise placed. Once the non-linear material has been deposited, implantation regions are formed within the non-linear material using an implantation process. The implantation regions are removed using an etching process, and electrodes are formed to the remaining material.
    Type: Application
    Filed: August 11, 2023
    Publication date: February 13, 2025
    Inventors: Su-Chun Yang, Chen Chiang Yu, Jui Hsuan Tsai, Jih-Churng Twu, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20250052962
    Abstract: A photonic assembly includes a composite die. The composite die includes: a photonic integrated circuits (PIC) die including waveguides and photonic devices therein; an electronic integrated circuits (EIC) die including semiconductor devices therein; and an embedded optical connector die contacting a top surface of the PIC die and laterally spaced from the EIC die.
    Type: Application
    Filed: January 2, 2024
    Publication date: February 13, 2025
    Inventors: Chen-Hua Yu, Hsing-Kuo Hsia, Chih-Wei Tseng, Jiun Yi Wu
  • Patent number: 12220461
    Abstract: A polypeptide-coupled small molecule compound and its antiviral applications are provided. The polypeptide-coupled small molecule compound is obtained by linking a polypeptide with a sequence X?nLXGG and a small molecule compound capable of inhibiting activity of papain-like protease (PLpro) of coronavirus through a chemical bond. The polypeptide with the sequence X?nLXGG is a polypeptide with a sequence LXGG at its carboxyl terminal, X and X? are independently any amino acid, and n is an integer between 1-50. The structure of the small molecule compound capable of inhibiting the activity of PLpro contains an amino group or a hydroxyl group. The polypeptide-coupled small molecule compound can inhibit the PLpro of SARS-CoV-2 in a targeted manner, thereby inhibiting the polyprotein cleavage of coronavirus in the host, and achieving the purpose of inhibiting the replication of coronavirus in the host. It has the advantages of synergistic inhibition, low cytotoxicity and favorable solubility.
    Type: Grant
    Filed: May 17, 2024
    Date of Patent: February 11, 2025
    Assignee: Guangzhou Medical University
    Inventors: Xiyong Yu, Ao Shen, Hua Tao, Lixin Zhao, Nanshan Zhong, Qiulian Zhu
  • Patent number: 12222545
    Abstract: An integrated circuit package and a method of forming the same are provided. The integrated circuit package includes a photonic integrated circuit die. The photonic integrated circuit die includes an optical coupler. The integrated circuit package further includes an encapsulant encapsulating the photonic integrated circuit die, a first redistribution structure over the photonic integrated circuit die and the encapsulant, and an opening extending through the first redistribution structure and exposing the optical coupler.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: February 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hsuan Tai, Chung-Ming Weng, Hung-Yi Kuo, Cheng-Chieh Hsieh, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 12224276
    Abstract: A semiconductor package includes a first die, a first heat conduction block and a first encapsulant. The first die has a bottom surface, a top surface and a sidewall between the bottom surface and the top surface. The first heat conduction block has a bottom surface, a top surface and a sidewall between the bottom surface and the top surface. The first encapsulant is disposed between the sidewall of the first die and the sidewall of the first heat conduction block.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: February 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chun-Hui Yu, Kuo-Chung Yee, Liang-Ju Yen
  • Patent number: 12224247
    Abstract: A fan-out package having a main die and a dummy die side-by-side is provided. A molding material is formed along sidewalls of the main die and the dummy die, and a redistribution layer having a plurality of vias and conductive lines is positioned over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die.
    Type: Grant
    Filed: March 26, 2024
    Date of Patent: February 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yan-Fu Lin, Chen-Hua Yu, Meng-Tsan Lee, Wei-Cheng Wu, Hsien-Wei Chen
  • Publication number: 20250044270
    Abstract: A system for notifying environmental pollution status includes wireless environment sensing devices and a portable wireless environmental pollution status notification device. The wireless environment sensing devices, respectively arranged in the different sensing locations of a physical environment, respectively store the sensing locations and respectively sense pollution related information corresponding to the different sensing locations to output the pollution related information and the sensing locations corresponding thereto. The portable wireless environmental pollution status notification device, wirelessly connected to the plurality of wireless environment sensing devices and located in the physical environment, receives the pollution related information and the sensing locations corresponding thereto and generates notification signals based on the pollution related information and the sensing locations corresponding thereto.
    Type: Application
    Filed: July 15, 2024
    Publication date: February 6, 2025
    Inventors: CHIA-JUI YANG, HERMAN CHUNGHWA RAO, CHUN-CHIEH KUO, HUA-PEI CHIANG, SHUI-SHU HSIAO, ZHENG-XIANG CHANG, CHYI-DAR JANG, TSUNG-JEN WANG, CHE-YU LIAO, CHIH-MIN CHAN, TENG-CHIEH YANG, CHANG-HUNG HSU
  • Publication number: 20250046744
    Abstract: A semiconductor device comprising a first semiconductor component and a composite bonding layer on the first semiconductor component. The composite bonding layer comprises a dielectric stress buffer layer and a dielectric planarization layer, wherein a hardness of the dielectric stress buffer layer is greater than a hardness of the dielectric planarization layer. The semiconductor device further includes a second semiconductor component bonded to the first semiconductor component by insulator-to-insulator bonding between the composite bonding layer and an insulating bonding layer on the second semiconductor component, wherein the dielectric planarization layer is disposed an interface between the composite bonding layer and the insulating bonding layer.
    Type: Application
    Filed: November 17, 2023
    Publication date: February 6, 2025
    Inventors: Chen-Hua Yu, Tung-Liang Shao
  • Publication number: 20250044517
    Abstract: A package includes an optical engine attached to a package substrate, wherein the optical engine includes a first waveguide; and a waveguide structure attached to the package substrate adjacent the optical engine, wherein the waveguide structure includes a second waveguide within a transparent block, wherein a first end of the second waveguide is optically coupled to the first waveguide, wherein the waveguide structure is configured to be connected to an optical fiber component such that a second end of the second waveguide is optically coupled to an optical fiber of the optical fiber component.
    Type: Application
    Filed: August 3, 2023
    Publication date: February 6, 2025
    Inventors: Chao-Jen Wang, Szu-Wei Lu, Tsung-Fu Tsai, Chen-Hua Yu
  • Patent number: 12218089
    Abstract: A semiconductor device includes a first die, a second die on the first die, and a third die on the second die, the second die being interposed between the first die and the third die. The first die includes a first substrate and a first interconnect structure on an active side of the first substrate. The second die includes a second substrate, a second interconnect structure on a backside of the second substrate, and a power distribution network (PDN) structure on the second interconnect structure such that the second interconnect structure is interposed between the PDN structure and the second substrate.
    Type: Grant
    Filed: January 12, 2023
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Chih-Hang Tung
  • Patent number: 12218026
    Abstract: A package structure and method of manufacturing is provided, whereby heat dissipating features are provided for heat dissipation. Heat dissipating features include conductive vias formed in a die stack, thermal chips, and thermal metal bulk, which can be bonded to a wafer level device. Hybrid bonding including chip to chip, chip to wafer, and wafer to wafer provides thermal conductivity without having to traverse a bonding material, such as a eutectic material. Plasma dicing the package structure can provide a smooth sidewall profile for interfacing with a thermal interface material.
    Type: Grant
    Filed: June 12, 2023
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen
  • Patent number: 12218006
    Abstract: Systems, devices and methods of manufacturing a system on silicon wafer (SoSW) device and package are described herein. A plurality of functional dies is formed in a silicon wafer. Different sets of masks are used to form different types of the functional dies in the silicon wafer. A first redistribution structure is formed over the silicon wafer and provides local interconnects between adjacent dies of the same type and/or of different types. A second redistribution structure may be formed over the first redistribution layer and provides semi-global and/or global interconnects between non-adjacent dies of the same type and/or of different types. An optional backside redistribution structure may be formed over a second side of the silicon wafer opposite the first redistribution layer. The optional backside redistribution structure may provide backside interconnects between functional dies of different types.
    Type: Grant
    Filed: November 7, 2023
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hua Yu, Wei Ling Chang, Chuei-Tang Wang, Tin-Hao Kuo, Che-Wei Hsu
  • Patent number: 12218022
    Abstract: A method includes forming a first passivation layer, forming a metal pad over the first passivation layer, forming a planarization layer having a planar top surface over the metal pad, and patterning the planarization layer to form a first opening. A top surface of the metal pad is revealed through the first opening. The method further includes forming a polymer layer extending into the first opening, and patterning the polymer layer to form a second opening. The top surface of the metal pad is revealed through the second opening.
    Type: Grant
    Filed: July 20, 2023
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsiu Chen, Wen-Chih Chiou, Chen-Hua Yu
  • Patent number: 12217976
    Abstract: A method of fabrication a package and a stencil structure are provided. The stencil structure includes a first carrier having a groove and stencil units placed in the groove of the first carrier. At least one of the stencil units is slidably disposed along sidewalls of another stencil unit. Each of the stencil units has openings.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Yi Wu, Chen-Hua Yu
  • Patent number: 12218706
    Abstract: This application discloses a signal generating method, apparatus, and system. One example method includes: performing cyclic electro-optic modulation on a first signal to generate a first optical frequency comb signal, where the first signal is a signal output by a laser source, the first optical frequency comb signal includes a target spectral component, and a frequency of the target spectral component is equal to a sum of or a difference between a frequency of the first signal and a frequency of a target signal; performing first filtering processing on the first optical frequency comb signal to generate the target spectral component; and generating the target signal based on a heterodyne beat frequency of the first signal and the target spectral component.
    Type: Grant
    Filed: December 8, 2022
    Date of Patent: February 4, 2025
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Songlin Shuai, Xianbin Yu, Zijie Lu, Hua Cai, Guangjian Wang
  • Patent number: 12218093
    Abstract: A system and method for connecting semiconductor dies is provided. An embodiment comprises connecting a first semiconductor die with a first width to a second semiconductor die with a larger second width and that is still connected to a semiconductor wafer. The first semiconductor die is encapsulated after it is connected, and the encapsulant and first semiconductor die are thinned to expose a through substrate via within the first semiconductor die. The second semiconductor die is singulated from the semiconductor wafer, and the combined first semiconductor die and second semiconductor die are then connected to another substrate.
    Type: Grant
    Filed: June 12, 2023
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Fa Chen, Chen-Hua Yu, Sen-Bor Jan