Abstract: A semiconductor device includes a photonic die and an optical die. The photonic die includes a grating coupler and an optical device. The optical device is connected to the grating coupler to receive radiation of predetermined wavelength incident on the grating coupler. The optical die is disposed over the photonic die and includes a substrate with optical nanostructures. Positions and shapes of the optical nanostructures are such to perform an optical transformation on the incident radiation of predetermined wavelength when the incident radiation passes through an area of the substrate where the optical nanostructures are located. The optical nanostructures overlie the grating coupler so that the incident radiation of predetermined wavelength crosses the optical die where the optical nanostructures are located before reaching the grating coupler.

Abstract: A method includes placing an electronic die and a photonic die over a carrier, with a back surface of the electronic die and a front surface of the photonic die facing the carrier. The method further includes encapsulating the electronic die and the photonic die in an encapsulant, planarizing the encapsulant until an electrical connector of the electronic die and a conductive feature of the photonic die are revealed, and forming redistribution lines over the encapsulant. The redistribution lines electrically connect the electronic die to the photonic die. An optical coupler is attached to the photonic die. An optical fiber attached to the optical coupler is configured to optically couple to the photonic die.

Abstract: A device includes a first redistribution structure comprising a first conductive line and a second conductive line. An integrated circuit die is attached to the first redistribution structure. A first via is coupled to the first conductive line on a first side, and a first conductive connector is coupled to the first conductive line on a second side opposite the first side. A second via is coupled to the second conductive line on the first side, and a second conductive connector is coupled to the second conductive line on the second side. The first via directly contacts the first conductive line without directly contacting the first conductive connector. The second via directly contacts the second conductive line and directly contacts the second conductive connector.

Abstract: A package assembly and a manufacturing method thereof are provided. The package assembly includes a first package component and an optical signal port disposed aside the first package component. The first package component includes a first die including an electronic integrated circuit, a first insulating encapsulation laterally covering the first die, a redistribution structure disposed on the first die and the first insulating encapsulation, and a second die including a photonic integrated circuit and electrically coupled to the first die through the redistribution structure. The optical signal port is optically coupled to an edge facet of the second die of the first package component.

Abstract: A semiconductor structure includes system-on-integrated chips, a first redistribution circuit structure and first conductive terminals. The system-on-integrated chips each include a die stack having two or more than two tiers, and each tier includes at least one semiconductor die. The first redistribution circuit structure is located on and electrically connected to the system-on-integrated chips. The first conductive terminals are connected on the first redistribution circuit structure, where the first redistribution circuit structure is located between the system-on-integrated chips and the first conductive terminals.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die; and a redistribution structure including: a plurality of dielectric layers over the encapsulant and the integrated circuit die; a plurality of metallization patterns in the dielectric layers, the metallization patterns being electrically coupled to the integrated circuit die; and a sealing ring in the dielectric layers, the sealing ring extending around the metallization patterns, the sealing ring being electrically isolated from the metallization patterns and the integrated circuit die, the sealing ring including a plurality of sealing ring layers, each of the sealing ring layers including a via portion extending through a respective one of the dielectric layers, the via portion of each of the sealing ring layers being aligned along a same common axis.

Abstract: A semiconductor device includes a substrate. Semiconductor layers are stacked one above another over the substrate. A gate structure wraps around each of the semiconductor layers. Epitaxial layers are over the substrate and in contact with opposite ends of a bottommost one of the semiconductor layers. Source/drain epitaxial structures are over and in contact with the epitaxial layers, respectively. Dielectric structures vertically between the epitaxial layers and the respective source/drain epitaxial structures, respectively.

Abstract: Optical devices and methods of manufacture are presented in which interposers are incorporated with optical devices. In some embodiments a method includes embedding first optical packages within the interposers in order to provide optical bridging between different semiconductor devices. The first optical packages may be embedded with a glass core or metallization layers.

Abstract: An embodiment photonic device may include a dielectric waveguide having a core portion, a cladding portion, and a first photonic coupler. The first photonic coupler may include a first dielectric pillar formed at a first surface of the cladding portion and optically coupled to the core portion, and a first dielectric cap optically coupled to the first dielectric pillar. Each of the first dielectric pillar and the first dielectric cap may include a polymer material that is transparent to infrared radiation such that radiation incident on the first dielectric cap from the core portion is focused by the first dielectric cap to a beam width that is smaller than a width of the core portion of the dielectric waveguide. Some embodiments may include a second photonic coupler having a second dielectric pillar optically coupled to the core portion, and a second dielectric cap optically coupled to the second dielectric pillar.

Abstract: An electronic package is provided, in which a circuit board and a circuit block are embedded in an encapsulating layer at a distance to each other, and circuit structures are formed on the two opposite surfaces of the encapsulating layer with electronic components arranged on one of the circuit structures. The circuit block and the circuit board embedded in the encapsulating layer are spaced apart from each other to allow to separate current conduction paths. As such, the circuit board will not overheat, and issues associated with warpage of the circuit board can be eliminated. Moreover, by embedding the circuit block and the circuit board in the encapsulating layer at a distance to each other, the structural strength of the encapsulating layer can be improved.

Abstract: A package structure includes a wafer-form semiconductor package and a thermal dissipating system. The wafer-form semiconductor package includes semiconductor dies electrically connected with each other. The thermal dissipating system is located on and thermally coupled to the wafer-form semiconductor package, where the thermal dissipating system has a hollow structure with a fluidic space, and the fluidic space includes a ceiling and a floor. The thermal dissipating system includes at least one inlet opening, at least one outlet opening and a plurality of first microstructures. The at least one inlet opening and the at least one outlet opening are spatially communicated with the fluidic space. The first microstructures are located on the floor, and at least one of the first microstructures is corresponding to the at least one outlet opening.

Abstract: A package structure includes at least one integrated circuit component, an insulating encapsulation, and a redistribution structure. The at least one integrated circuit component includes a semiconductor substrate, an interconnection structure disposed on the semiconductor substrate, and signal terminals and power terminals located on and electrically connecting to the interconnection structure. The interconnection structure is located between the semiconductor substrate and the signal terminals and between the semiconductor substrate and the power terminals, and where a size of the signal terminals is less than a size of the power terminals. The insulating encapsulation encapsulates the at least one integrated circuit component. The redistribution structure is located on the insulating encapsulation and electrically connected to the at least one integrated circuit component.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes etching a source/drain recess in a semiconductor substrate and performing an epitaxy process to form a source/drain epitaxial structure in the source/drain recess. The epitaxy process comprises a plurality of cycles, each of the cycles comprises depositing a semiconductor material by introducing a plasma-phase precursor and a gas-phase precursor to the semiconductor substrate.

Abstract: An electrical discharge machining equipment with equal-energy density comprises an electrode, a parameter database, a signal capturing device and a controller. The parameter database stores an equal-energy density sheet comprising a plurality of processing parameter sets. Each processing parameter set is corresponding to a material removed volume and comprises a discharge energy, a discharge parameter, a feed rate and an energy density. The signal capturing device detects a first discharge parameter of the electrode during machining a work piece. The controller selects a first feed rate to control the electrode. When the first discharge parameter changes to a second discharge parameter, the controller calculates a material volume of the workpiece according to the second discharge parameter and the equal-energy density sheet, and selects a second feed rate according to the material volume, the material removed volume and the equal-energy density sheet to control the electrode for processing the workpiece.

Abstract: A method of forming a semiconductor package includes: bonding a first wafer to a second wafer, where the first wafer includes a plurality of electronic dies, and the second wafer includes a plurality of photonic dies; after bonding the first wafer, forming trenches in the second wafer between adjacent ones of the plurality of photonic dies; filling the trenches with an optical glue; and dicing the first wafer and the second wafer to form a plurality of photonic packages, where a photonic package of the plurality of photonic packages includes an electronic die, a photonic die bonded to the electronic die, and the optical glue, where the optical glue extends along a sidewall of the photonic package.

Abstract: A semiconductor structure includes a first redistribution structure, a first local interconnect component disposed on the first redistribution structure, and a first interconnect structure over a second side of the first local interconnect component. The first local interconnect component includes a first plurality of redistribution layers. The first plurality of redistribution layers includes a first plurality of conductive features on a first side of the first local interconnect component. Each of the first plurality of conductive features are coupled to respective conductive features of the first redistribution structure. The first interconnect structure includes a second plurality of conductive features and a third plurality of conductive features. The second plurality of conductive features are electrically coupled to the third plurality of conductive features through the first local interconnect component.

Abstract: A method of manufacturing a semiconductor device includes applying a polymer mixture over a substrate, exposing and developing at least a portion of the polymer mixture to form a developed dielectric, and curing the developed dielectric to form a dielectric layer. The polymer mixture includes a polymer precursor, a photosensitizer, and a solvent. The polymer precursor may be a polyamic acid ester.

Abstract: A structure including a first semiconductor die and a second semiconductor die is provided. The first semiconductor die includes a first bonding structure. The first bonding structure includes a first dielectric layer and first conductors embedded in the first dielectric layer. The second semiconductor die includes a second bonding structure. The second bonding structure includes a second dielectric layer and second conductors embedded in the second dielectric layer. The first dielectric layer is in contact with the second dielectric layer, and the first conductors are in contact with the second conductors. Thermal conductivity of the first dielectric layer and the second dielectric layer is greater than thermal conductivity of silicon dioxide.

Abstract: An optical waveguide includes a first portion, a second portion, and a third portion. The first portion includes an input port configured to allow an input optical signal of a first propagation direction entering therefrom. The second portion includes a taper waveguide portion configured to expanding the input optical signal and a rectangular waveguide portion configure to split the input optical signal, where the rectangular waveguide portion is connected to the taper waveguide portion. The third portion includes at least one output port configured to allow an output optical signal of an output propagation direction exiting therefrom, where the output propagation direction is different from the first propagation direction. The second portion is sandwiched between the first portion and the third portion.

Abstract: An embodiment package comprises an integrated circuit die encapsulated in an encapsulant, a patch antenna over the integrated circuit die, and a dielectric feature disposed between the integrated circuit die and the patch antenna. The patch antenna overlaps the integrated circuit die in a top-down view. The thickness of the dielectric feature is in accordance with an operating bandwidth of the patch antenna.