Patents by Inventor Huai-Yuan Tseng

Huai-Yuan Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11062780
    Abstract: Method(s) and structure(s) for a two-page read operation are described and provide a multiple page read. The two page read operation provides for reading two pages with in a block without reducing the control gates to a low voltage level. The two page read can read the first page using an incrementing voltage level at discrete steps and starting the second page read at the high state for the control gates from the first page read. The second page read then decrements the control gate voltages level through the steps. This should reduce energy consumption. The two-page read operation will also reduce the time as the time period to reset the control gates to a low state are not required in between the page read operations.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: July 13, 2021
    Inventors: Zhiping Zhang, Huai-Yuan Tseng, Jiahui Yuan, Dengtao Zhao, Deepanshu Dutta
  • Publication number: 20210202011
    Abstract: Method(s) and structure(s) for a two-page read operation are described and provide a multiple page read. The two page read operation provides for reading two pages with in a block without reducing the control gates to a low voltage level. The two page read can read the first page using an incrementing voltage level at discrete steps and starting the second page read at the high state for the control gates from the first page read. The second page read then decrements the control gate voltages level through the steps. This should reduce energy consumption. The two-page read operation will also reduce the time as the time period to reset the control gates to a low state are not required in between the page read operations.
    Type: Application
    Filed: December 30, 2019
    Publication date: July 1, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Zhiping Zhang, Huai-Yuan Tseng, Jiahui Yuan, Dengtao Zhao, Deepanshu Dutta
  • Patent number: 11037635
    Abstract: Apparatuses and techniques are described for managing power consumption in a memory device. When a multi-plane read command is received, a control circuit determines whether the blocks identified by the read command are fully or partially programmed. If they are fully programmed, the read command is executed while applying a common read pass voltage to the unprogrammed word lines of the respective blocks. If the blocks are not all fully programmed, the control circuit determines a last-programmed word line. If the last-programmed word lines are not equal in each block, the read command is executed while applying a base read pass voltage to the unprogrammed word lines of one or more higher-programmed blocks and a lower read pass voltage to the unprogrammed word lines of one or more lower-programmed blocks.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: June 15, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Yu-Chung Lien, Tomer Eliash, Huai-Yuan Tseng
  • Patent number: 11024393
    Abstract: An apparatus comprises a driver circuit, sense circuit, and die controller. The driver circuit supplies a pass voltage to a selected word line and unselected word lines, a sense voltage to an adjacent word line, and a bit line voltage to bit lines coupled to selected and unselected word lines. The sense circuit determines nonconducting and conducting memory cells on the adjacent word line. The die controller then directs the driver circuit to ramp the sense voltage on the adjacent word line to the pass voltage and ramp the pass voltage on the selected word line to ground. The die controller then directs the driver circuit to ramp the bit line voltage for bit lines coupled to nonconducting memory cells to a bit line compensation voltage and directs the sense circuit to read memory cells of the selected word line based on the bit line compensation voltage.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: June 1, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Zhiping Zhang, Huai-Yuan Tseng, Ken Oowada, Deepanshu Dutta
  • Patent number: 11017869
    Abstract: Techniques are provided to adaptively determine when to begin verify tests for memory cells during a program operation. The memory cells are programmed using a normal programming speed until their threshold voltage exceeds an initial verify voltage. The memory cells are then programmed further using a reduced programming speed until their threshold voltage exceeds a final verify voltage. In one aspect, a count of memory cells which exceeds the initial verify voltage is used to determine when to begin verify tests for a higher data state. In another aspect, a count of the higher state memory cells which exceeds the initial or final verify voltage is used to determine when to begin verify tests for the higher data state. The counted memory cells are not subject to the reduced programming speed.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: May 25, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Huai-Yuan Tseng, Deepanshu Dutta
  • Publication number: 20210134370
    Abstract: A method of concurrently programming a memory. Various methods include: applying a non-negative voltage on a first bit line coupled to a first memory cell; applying a negative voltage on a second bit line coupled to a second memory cell, where the negative voltage is generated using triple-well technology; then applying a programming pulse to the first and second memory cells concurrently; and in response, programming the first and second memory cells to different states. The methods also include applying a quick pass write operation to the first and second memory cells, by: applying a quick pass write voltage to the first bit line coupled to the first memory cell, where the quick pass write voltage is higher than the non-negative voltage; applying a negative quick pass write voltage to the second bit line coupled to the first memory cell, where the negative quick pass write voltage is generated using triple-well technology.
    Type: Application
    Filed: December 3, 2019
    Publication date: May 6, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Zhiping Zhang, Muhammad Masuduzzaman, Huai-Yuan Tseng, Dengtao Zhao, Deepanshu Dutta
  • Publication number: 20210134369
    Abstract: A method of concurrently programming a memory. Various methods include: applying a non-negative voltage on a first bit line coupled to a first memory cell; applying a negative voltage on a second bit line coupled to a second memory cell, where the negative voltage is generated using triple-well technology; then applying a programming pulse to the first and second memory cells concurrently; and in response, programming the first and second memory cells to different states. The methods also include applying a quick pass write operation to the first and second memory cells, by: applying a quick pass write voltage to the first bit line coupled to the fist memory cell, where the quick pass write voltage is higher than the non-negative voltage; applying a negative quick pass write voltage to the second bit line coupled to the first memory cell, where the negative quick pass write voltage is generated using triple-well technology.
    Type: Application
    Filed: October 30, 2019
    Publication date: May 6, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Zhiping Zhang, Muhammad Masuduzzaman, Huai-Yuan Tseng, Dengtao Zhao, Deepanshu Dutta
  • Publication number: 20210134372
    Abstract: A method reading memory using bi-directional sensing, including programming first memory cells coupled to a first word-line using a normal programming order; programming second memory cells coupled to a second word-line using a normal programming order; reading data from the first memory cells by applying a normal sensing operation to the first word-line; and reading data from the second memory cells by applying a reverse sensing operation to the second word-line. Methods also include receiving an error associated with reading data from the first memory cells; and then reading the data from the first memory cells by applying a reverse sensing operation to the first word-line. Method also include receiving an error associated with reading the data from the second memory cells; and then reading the data from the second memory cells by applying a normal sensing operation to the second word-line.
    Type: Application
    Filed: November 6, 2019
    Publication date: May 6, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Zhiping Zhang, Muhammad Masuduzzaman, Huai-Yuan Tseng, Peng Zhang, Dengtao Zhao, Deepanshu Dutta
  • Patent number: 10984867
    Abstract: A memory apparatus and method of operation are provided. The apparatus includes first memory cells coupled to control circuit and a particular word line and storing a first cell data. The apparatus also includes second memory cells coupled to a source side neighbor word line disposed on a source side of the particular word line and storing second cell threshold voltages programmed after the first cell data. The control circuit senses the second cell threshold voltages at a first time while applying a predetermined initial read voltage to the source side neighbor word line. The control circuit senses the first cell data at a second time while iteratively applying one of a plurality of particular read voltages to the particular word line and simultaneously and iteratively applying one of a plurality of neighbor pass voltages to the source side neighbor word line based on the second cell threshold voltages.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: April 20, 2021
    Assignee: SanDiskTechnologies LLC
    Inventors: Zhiping Zhang, Sarath Chandran Puthen Thermadam, Huai-Yuan Tseng, Deepanshu Dutta
  • Patent number: 10930355
    Abstract: A methodology and structure for accounting for fabrication difference in memory holes is described. Increasing the distance of the memory holes from the sources of etchant or other fabrication material results in different characteristics of the memory from the outer memory holes to the inner memory holes. These difference can be accounted for by grouping the memory holes and altering the parameters of the program or verify operations based on the groupings. The bitline voltage for the inner grouping can be less than the bitline voltage for the outer groupings. The sense timing can be greater for the outer groupings relative to the inner groupings. This can result in voltage threshold for the inner groupings and outer groupings overlying each other to improve memory performance.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: February 23, 2021
    Assignee: SanDiskTechnologies LLC
    Inventors: Xiang Yang, Huai-yuan Tseng, Deepanshu Dutta
  • Patent number: 10910075
    Abstract: Techniques are provided to adaptively determine when to begin verify tests for memory cells during a program operation. The memory cells are programmed using a normal programming speed until their threshold voltage exceeds an initial verify voltage. The memory cells are then programmed further using a reduced programming speed until their threshold voltage exceeds a final verify voltage. In one aspect, a count of memory cells which exceeds the initial verify voltage is used to determine when to begin verify tests for a higher data state. In another aspect, a count of the higher state memory cells which exceeds the initial or final verify voltage is used to determine when to begin verify tests for the higher data state. The counted memory cells are not subject to the reduced programming speed.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: February 2, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Huai-Yuan Tseng, Deepanshu Dutta
  • Patent number: 10902925
    Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells arranged in strings and connected to word lines overlying one another in a stack. The apparatus includes a control circuit configured to determine whether the memory cells of the block are all programmed. The control circuit determines a boundary word line splitting the word lines into first and second word line sets connected to the memory cells that are respectively programmed and not programmed in response to determining the memory cells of the block are not all programmed. The control circuit applies a delta adjusted read voltage being a default read pass voltage minus a delta voltage to a subset of the second word line set separated from the boundary word line in the stack by at least an offset number of the word lines while reading a first group of memory cells.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: January 26, 2021
    Assignee: SanDiskTechnologies LLC
    Inventors: Yu-Chung Lien, Michael Huai-Yuan Tseng, Deepanshu Dutta
  • Patent number: 10885994
    Abstract: A circuit includes a program controller configured to perform a program operation with interleaved program-verify loops to program memory cells in a same block. During each program-verify loop, a control gate line voltage supply circuit first supplies a program pulse to a first cell of the block and then, before verifying the first cell, supplies a program pulse to a second cell of the block. After the program pulses are sent, the control gate line supply circuit consecutively supplies verify pulses to the first cell and the second cell such that a delay is introduced between the respective program and verify stages of the first and second cells. Additionally, a constant voltage bias on common control gate lines of the first and second memory cells is applied during the consecutive verify stages. Further, an order of verify pulses may be applied in a reverse order during a verify stage.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: January 5, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Huai-Yuan Tseng, Deepanshu Dutta
  • Publication number: 20200388343
    Abstract: A method and system for executing a dynamic 1-tier scan on a memory array are provided. The memory array includes a plurality of memory cells organized into a plurality of sub-groups. The dynamic 1-tier scan includes executing an program loop in which cells of a first sub-group are counted to determine whether a numeric threshold is met, and, if the numeric threshold is met with respect to the first sub group, at least one additional program loop is executed in which cells of a second sub-group are counted to determine whether the numeric threshold is met with respect to the second sub-group.
    Type: Application
    Filed: June 24, 2020
    Publication date: December 10, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Xiang Yang, Deepanshu Dutta, Huai-yuan Tseng
  • Publication number: 20200388338
    Abstract: A methodology and structure for accounting for fabrication difference in memory holes is described. Increasing the distance of the memory holes from the sources of etchant or other fabrication material results in different characteristics of the memory from the outer memory holes to the inner memory holes. These difference can be accounted for by grouping the memory holes and altering the parameters of the program or verify operations based on the groupings. The bitline voltage for the inner grouping can be less than the bitline voltage for the outer groupings. The sense timing can be greater for the outer groupings relative to the inner groupings. This can result in voltage threshold for the inner groupings and outer groupings overlying each other to improve memory performance.
    Type: Application
    Filed: June 5, 2019
    Publication date: December 10, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Xiang Yang, Huai-yuan Tseng, Deepanshu Dutta
  • Patent number: 10861537
    Abstract: Techniques are provided for operating non-volatile storage. Peak current consumption may be reduced in connection with sensing non-volatile memory cells. Peak current consumption may be reduced when a first read condition is present. In one aspect, the value of a parameter of a voltage that is applied to a word line during a pre-read phase of a sense operation is controlled in order to reduce peak current consumption when the first read condition is present. Examples of the parameter include a ramp rate, a number of intermediate voltage levels, and a start time.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: December 8, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Yu-Chung Lien, Huai-Yuan Tseng, Deepanshu Dutta, Abhijith Prakash
  • Patent number: 10839922
    Abstract: An apparatus includes an array of memory cells comprising a first sub-block and a second sub-block electrically coupled by a channel. The apparatus also includes a measurement circuit configured to take a first measurement of a first sub-block of memory cells at a first offset threshold and a second measurement of the first sub-block of memory cells at a second offset threshold. The apparatus further includes a detection circuit configured to detect a disturb condition of the first sub-block based on at least one of the first measurement and the second measurement, and to initiate data maintenance in response to the disturb condition of the first sub-block.
    Type: Grant
    Filed: May 26, 2018
    Date of Patent: November 17, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Huai-Yuan Tseng, Deepanshu Dutta
  • Patent number: 10832778
    Abstract: A methodology and structure for driving a selected wordline to a negative voltage without the need for a negative wordline voltage generator. The methodology includes the step of boosting a non-selected wordline to a first positive voltage. The methodology proceeds with holding a selected wordline, which is adjacent to and capacitively coupled with the non-selected wordline, at zero voltage. The methodology continues with floating the selected wordline. The methodology proceeds with driving the non-selected wordline to a lower voltage to shift the selected wordline to less than zero volts due to capacitance effects. The methodology continues with the step of accelerating charge loss in a defective memory cell connected to the selected wordline while at a negative voltage during a soft erase operation.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: November 10, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Huai-yuan Tseng, Deepanshu Dutta
  • Patent number: 10811089
    Abstract: Apparatuses, systems, and methods are disclosed for adjusting a programming setting such as a programming voltage of a set of non-volatile storage cells, such as an SLC NAND array. The non-volatile storage cells may be arranged into a plurality of word lines. A subset of the non-volatile storage cells may be configured to store a programming setting. An on-die controller may be configured to read the programming setting from the setting subset, and write data to the non-volatile storage cells, using the programming setting. The on-die controller may further be configured to determine that the programming setting causes suboptimal programming of one or more of the non-volatile storage cells, and in response to the determination, store a revised programming setting on the setting subset.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: October 20, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Huai-Yuan Tseng, Deepanshu Dutta
  • Publication number: 20200303025
    Abstract: Techniques are provided to adaptively determine when to begin verify tests for memory cells during a program operation. The memory cells are programmed using a normal programming speed until their threshold voltage exceeds an initial verify voltage. The memory cells are then programmed further using a reduced programming speed until their threshold voltage exceeds a final verify voltage. In one aspect, a count of memory cells which exceeds the initial verify voltage is used to determine when to begin verify tests for a higher data state. In another aspect, a count of the higher state memory cells which exceeds the initial or final verify voltage is used to determine when to begin verify tests for the higher data state. The counted memory cells are not subject to the reduced programming speed.
    Type: Application
    Filed: June 5, 2020
    Publication date: September 24, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Xiang Yang, Huai-Yuan Tseng, Deepanshu Dutta