Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and arranged in a plurality of planes. The apparatus also includes a control circuit coupled to the word lines and the bit lines and configured to determine whether a program operation of the memory cells involves all of the plurality of planes. In response to the program operation of the memory cells not involving all of the plurality of planes, the control circuit adjusts at least one of a bit line ramp rate of a bit line voltage applied to the bit lines and a word line ramp rate of at least one word line voltage applied to the word lines during the program operation based on a quantity of the plurality of planes associated with the memory cells being program-verified in the program operation.

Abstract: An apparatus includes a controller and a plurality of memory dies operable connected to and controlled by the controller. Each of the memory dies draws a current from a current source during a program operation. The controller being configured to receive a clock signal from each of the memory dies; count the number of clock signal received to determine a count value; and dynamically stagger at least one of the memory dies relative to the other memory dies when the count value reaches a maximum count value within a threshold time. The controller operates to dynamically stagger operation of at least one memory die to prevent the group of memory dies from operating synchronously.

Abstract: Apparatuses and techniques are described for avoiding current consumption peaks during a program operation for a memory device. The timing of scan operations of latches is adjusted to avoid overlapping with an increase in word line voltages. The scan operations can include a pre-charge select scan, which identifies memory cells subject to a verify test, and a fill operation for latches of memory cells which fail a verify test in a prior program loop. The pre-charge select scan can occur before the increase in the word line voltages, while the fill operation occurs after the increase in word line voltages. In another approach, the start of the increase in the word line voltages is delayed when a state bit scan is expected to take a relatively long time, e.g., when a verify test is passed in a prior program loop.

Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block having memory cells connected to word lines and arranged in strings and is divided into a first sub-block and a second sub-block each configured to be erased as a whole in an erase operation. The apparatus has a temperature measuring circuit configured to detect an ambient temperature of the apparatus. A control circuit is configured to determine a word line inhibit voltage based on the ambient temperature. The control circuit applies an erase voltage to each of the strings while simultaneously applying a word line erase voltage to the word lines associated with a selected one of the first and second sub-blocks to encourage erasing and the word line inhibit voltage to the word lines associated with an unselected one of the first and second sub-blocks to discourage erasing in the erase operation.

Abstract: Apparatus and methods are described to program memory cells and verify stored values programmed into the cells. The next stage in stored memory can be moved to the current verification iteration when certain conditions are met. Verification can include counting bits that exceed a voltage value for a stage being verified to produce a bit count number and determining if the bit count number for the stage being verified meets a threshold value. If the bit count number does not meet the threshold, the verification process can continue with a current verify iteration and thereafter move to a next verify iteration. If the bit count number does meet the threshold, the process can add a next stage to the current verify iteration and thereafter move to a next verify iteration.

Abstract: A method of performing an erase operation on non-volatile storage is disclosed. The method comprises: applying, in a first erase loop of a plurality of erase loops of the erase operation, a first erase voltage pulse to a set of non-volatile storage elements; determining an upper tail of a threshold voltage distribution of the set of non-volatile storage elements after applying the first erase voltage pulse; determining a second erase voltage pulse based on the upper tail of the threshold voltage distribution of the set of non-volatile storage elements; and applying, in a second erase loop of the plurality of erase loops, the second erase voltage pulse to the set of non-volatile storage elements.

Abstract: A storage device is disclosed. The storage device is configured to: determine data states for a first set of memory cells of a first neighboring word line of the and a second set of memory cells of a second neighboring word line, the first and the second neighboring word lines being adjacent to a selected word line; identify a zone of a plurality of zones for each data state combination of the data states, each data state combination comprising a data state of a memory cell of the first set of memory cells and a data state of a memory cell of the second set of memory cells, each zone of the plurality of zones corresponding to a data retention compensation scheme; and perform a read operation on the selected word line including applying each data retention compensation scheme corresponding to any zones identified.

Abstract: To improve the erase process, multiple methods of erasing are utilized. A first method of erasing is relied on at the beginning of life of the memory system. A second method is increasingly relied on as the memory system is used and undergoes many program/erase cycles. In one example, the first method of erase includes applying an erase enable voltage separately to different subsets of the word lines while word lines not receiving the erase enable voltage receive an erase inhibit voltage. In one example, the second method of erase includes applying an erase enable voltage concurrently to all subsets of the word lines.

Abstract: Apparatuses and techniques are described for performing an erase operation for a set of memory cells, where the erase operation applies a staircase or multi-level word line voltage concurrent with a fixed level erase pulse to provide multiple channel-to-gate voltages. Current consumption and time are saved compared to applying a multi-level erase voltage to a high capacitance substrate, for example. In one approach, the word line voltage is changed from a positive erase-enable voltage to a negative erase-enable voltage during the multi-level erase pulse. A step size of a next erase pulse can be set to achieve an approximately constant step increase in channel-to-gate voltages of the memory cells.

Abstract: Aspects of a storage device including a memory and a controller are provided which allow for reduction of current in open blocks during read operations using read voltage ramp rate control. The controller determines whether a block is open or closed. If the block is closed, the controller causes a read voltage to be applied to one of the block's word lines at a first ramp rate. If the block is open, the controller causes a read voltage to be applied to another of the block's word lines at a slower, second ramp rate. The controller further causes a read voltage to be applied to another word line of the open block at a different, third ramp rate. Thus, read voltages for open blocks may ramp slower than read voltages for closed blocks, as well as ramp at different rates for different word lines in open blocks.

Abstract: Aspects of a storage device including a memory and a controller are provided which allow for reduction of current during program operations using pre-charge timing control based on an inhibit bit line count acquired from data latches. When the inhibit bit line count is within a bit line count range, the controller pre-charges bit lines in memory during a first time period to a first target voltage, and when the inhibit bit line count is outside the bit line count range, the controller pre-charges the bit lines during a second, earlier time period to a second, smaller target voltage. The controller is thus configured to reduce current and minimize operation overlaps in the earlier time period during the middle of the program operation where current is highest. Thus, a balance in power consumption and performance may be achieved during program operations using timing control.

Abstract: An apparatus includes a memory controller configured to apply selected one or ones of the program verify voltage levels to a single tier of memory cells. A memory controller is configured to: program data into the plurality of memory cells; and perform a program verify operation across multiple voltage levels with a first voltage level of the program verify operation being applied to a single tier that represents all of the tiers in the memory group and a second voltage level of the program verify operation being applied to multiple tiers, wherein the first voltage level is less than the second voltage level. In embodiments, less than all of the tiers, e.g., two or four tiers, can be used in the program verify to represent all of the tires.

Abstract: A storage device is disclosed herein. The storage device comprises a block including a plurality of memory cells and a circuit coupled to the plurality of memory cells of the block. The circuit is configured to program memory cells of a plurality of strings of a word line of the block and verify, for a plurality of sets of the memory cells, a data state of a set of the memory cells, where each set of the plurality of sets of the memory cells includes a memory cell from each string of the plurality of strings of the word line. Further, the circuit is configured to determine a number of sets of the plurality of memory cell sets that are verified to be in a first data state and determine, based on the number of sets, whether the block is faulty.

Abstract: To improve the erase process, multiple methods of erasing are utilized. A first method of erasing is relied on at the beginning of life of the memory system. A second method is increasingly relied on as the memory system is used and undergoes many program/erase cycles. In one example, the first method of erase includes applying an erase enable voltage separately to different subsets of the word lines while word lines not receiving the erase enable voltage receive an erase inhibit voltage. In one example, the second method of erase includes applying an erase enable voltage concurrently to all subsets of the word lines.

Abstract: Apparatuses and techniques are described for reducing a peak current consumption during a program operation for a memory device. A higher current peak occurs in a first program loop of the program operation when a set of word lines is in a discharged state, also referred to as a first read condition. A current reduction countermeasure can be used when ramping up voltages of unselected word lines to a read pass voltage during the verify phase of the program loop. The countermeasure can involve reducing the ramp up rate, reducing the read pass voltage, or delaying the start of the ramp up for a portion of the word lines.

Abstract: Aspects of a storage device including a memory and a controller are provided which allow for reduction of current during program operations using pre-charge ramp rate control based on an inhibit bit line count acquired from data latches. When the inhibit bit line count is within a bit line count range, the controller pre-charges bit lines in memory at a first ramp rate to a first target voltage, and when the inhibit bit line count is outside the bit line count range, the controller pre-charges the bit lines at a second, faster ramp rate to a second, smaller target voltage. The inhibit bit line count may increase throughout a program operation, and the bit line count range may be configured for the middle of the program operation where current is typically high. Thus, a balance in power consumption and performance may be achieved during program operations using ramp rate control.

Abstract: A method for memory program verification includes performing a write operation on memory cells of a memory device. The method also includes identifying memory strings associated with respective memory cells of the memory cells. The method also includes identifying a first memory string of the memory strings. The method also includes disabling a portion of a write verification for the first memory string. The method also includes enabling the portion of the write verification for other memory strings of the memory strings. The method also includes performing at least the portion of the write verification operation on write verification enabled memory strings.

Abstract: Power and/or current regulation in non-volatile memory systems is disclosed. Peak power/current usage may be reduced by staggering concurrent program operations in the different semiconductor dies. Each set of one or more semiconductor dies has an earliest permitted start time for its program operation, as well as a number of permitted backup start times. The permitted start times are unique for each set of one or more semiconductor dies. There may be a uniform gap or delay between each permitted start time. If a semiconductor die is busy with another memory operation at or after its earliest permitted start time, then the program operation is initiated or resumed at one of the permitted backup times. By having permitted backup times, the memory system need not poll each semiconductor die to determine whether the semiconductor die is ready/busy in order to determine when a die should start a program operation.

Abstract: Apparatus and methods are described to program memory cells and verify stored values programmed into the cells. The next stage in stored memory can be moved to the current verification iteration when certain conditions are met. Verification can include counting bits that exceed a voltage value for a stage being verified to produce a bit count number and determining if the bit count number for the stage being verified meets a threshold value. If the bit count number does not meet the threshold, the verification process can continue with a current verify iteration and thereafter move to a next verify iteration. If the bit count number does meet the threshold, the process can add a next stage to the current verify iteration and thereafter move to a next verify iteration.

Abstract: An apparatus includes a memory controller configured to apply selected one or ones of the program verify voltage levels to a single tier of memory cells. A memory controller is configured to: program data into the plurality of memory cells; and perform a program verify operation across multiple voltage levels with a first voltage level of the program verify operation being applied to a single tier that represents all of the tiers in the memory group and a second voltage level of the program verify operation being applied to multiple tiers, wherein the first voltage level is less than the second voltage level. In embodiments, less than all of the tiers, e.g.