Patents by Inventor Huai-Yuan Tseng
Huai-Yuan Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180254090Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of the memory cells can shift depending on the coupled up state of the word lines. In one approach, for a read operation, a representative word line voltage in a block is detected and a corresponding set of read voltages is selected. In another approach, a pre-read voltage pulse is applied to a selected word line in response to a read command, just prior to reading the selected cells. In another approach, a voltage pulse is periodically applied to each word line in a block to provide the word lines in a coupled up state. In another approach, a soft erase is performed after a read operation to prevent coupling up of the word lines.Type: ApplicationFiled: November 17, 2017Publication date: September 6, 2018Applicant: SanDisk Technologies LLCInventors: Deepanshu Dutta, Idan Alrod, Huai-Yuan Tseng, Amul Desai, Jun Wan, Ken Cheah, Sarath Puthenthermadam
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Patent number: 10026492Abstract: Systems and methods for improving the reliability of data stored in memory cells are described. To mitigate the effects of trapped electrons after one or more programming pulses have been applied to memory cells, a delay between the one or more programming pulses and subsequent program verify pulses may be set based on a chip temperature, the number of the one or more programming pulses that were applied to the memory cells, and/or the programming voltage that was applied to the memory cells during the one or more programming pulses. To mitigate the effects of residual electrons after one or more program verify pulses have been applied to memory cells, a delay between the one or more program verify pulses and subsequent programming pulses may be set based on a chip temperature and/or the programming voltage to be applied to the memory cells during the subsequent programming pulses.Type: GrantFiled: July 2, 2017Date of Patent: July 17, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Deepanshu Dutta, Arash Hazeghi, Huai-Yuan Tseng, Cynthia Hsu, Navneeth Kankani
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Patent number: 10026486Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of the memory cells can shift depending on the coupled up state of the word lines. In one approach, for a read operation, a representative word line voltage in a block is detected and a corresponding set of read voltages is selected. In another approach, a pre-read voltage pulse is applied to a selected word line in response to a read command, just prior to reading the selected cells. In another approach, a voltage pulse is periodically applied to each word line in a block to provide the word lines in a coupled up state. In another approach, a soft erase is performed after a read operation to prevent coupling up of the word lines.Type: GrantFiled: March 6, 2017Date of Patent: July 17, 2018Assignee: SanDisk Technologies LLCInventors: Deepanshu Dutta, Idan Alrod, Huai-Yuan Tseng, Amul Desai, Jun Wan, Ken Cheah, Sarath Puthenthermadam
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Patent number: 10014063Abstract: Techniques are provided to adaptively determine when to begin verify tests for a particular data state based on a programming progress of a set of memory cells. A count is made in a program-verify iteration of memory cells which pass a verify test of a state N. The count is used to determine a subsequent program-verify iteration in which to perform a verify test of a higher state as a function of an amount by which the count exceeds a threshold count. In another approach, an optimum verify scheme is implemented on a per-group basis for groups of adjacent memory cells at different heights in a 3D memory device. In another approach, an optimum verify scheme is implemented on a per-layer basis for sets of memory cells at a common height or word line layer in a 3D memory device.Type: GrantFiled: October 30, 2015Date of Patent: July 3, 2018Assignee: SanDisk Technologies LLCInventors: Huai-Yuan Tseng, Deepanshu Dutta, Tai-Yuan Tseng, Grishma Shah, Muhammad Masuduzzaman
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Patent number: 9875805Abstract: A double lockout programming technique is provided having a hidden delay between programming and verification. A temporary lockout stage and a permanent lockout stage are provided for double lockout programming. The temporary lockout stage precedes the permanent lockout stage and is used to initially determine when a memory cell should be locked out a first time for one or more program pulses. When a memory cell initially passes verification for its target state, it is temporarily locked out from programming for one or more program pulses. The memory cell enters a permanent lockout stage where it is verified again for its target state. When the memory cell passes verification a second time, it is permanently locked out for programming during the current program phase. The memory cell may be programmed at one or more reduced program rates in the permanent lockout stage.Type: GrantFiled: October 30, 2015Date of Patent: January 23, 2018Assignee: SanDisk Technologies LLCInventors: Huai-Yuan Tseng, Deepanshu Dutta
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Publication number: 20170309344Abstract: Systems and methods for improving the reliability of data stored in memory cells are described. To mitigate the effects of trapped electrons after one or more programming pulses have been applied to memory cells, a delay between the one or more programming pulses and subsequent program verify pulses may be set based on a chip temperature, the number of the one or more programming pulses that were applied to the memory cells, and/or the programming voltage that was applied to the memory cells during the one or more programming pulses. To mitigate the effects of residual electrons after one or more program verify pulses have been applied to memory cells, a delay between the one or more program verify pulses and subsequent programming pulses may be set based on a chip temperature and/or the programming voltage to be applied to the memory cells during the subsequent programming pulses.Type: ApplicationFiled: July 2, 2017Publication date: October 26, 2017Applicant: SANDISK TECHNOLOGIES LLCInventors: Deepanshu Dutta, Arash Hazeghi, Huai-Yuan Tseng, Cynthia Hsu, Navneeth Kankani
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Patent number: 9721672Abstract: Systems and methods for improving the reliability of data stored in memory cells are described. To mitigate the effects of trapped electrons after one or more programming pulses have been applied to memory cells, a delay between the one or more programming pulses and subsequent program verify pulses may be set based on a chip temperature, the number of the one or more programming pulses that were applied to the memory cells, and/or the programming voltage that was applied to the memory cells during the one or more programming pulses. To mitigate the effects of residual electrons after one or more program verify pulses have been applied to memory cells, a delay between the one or more program verify pulses and subsequent programming pulses may be set based on a chip temperature and/or the programming voltage to be applied to the memory cells during the subsequent programming pulses.Type: GrantFiled: April 15, 2016Date of Patent: August 1, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Deepanshu Dutta, Arash Hazeghi, Huai-Yuan Tseng, Cynthia Hsu, Navneeth Kankani
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Patent number: 9711211Abstract: Based on performance during programming, the non-volatile memory cells are classified as fast programming memory cells and slow programming memory cells (or other classifications). At a separate time for each programmed state, threshold voltage distributions are compacted based on the classification.Type: GrantFiled: October 29, 2015Date of Patent: July 18, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Muhammad Masuduzzaman, Tai-Yuan Tseng, Huai-Yuan Tseng, Deepanshu Dutta
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Publication number: 20170178736Abstract: Systems and methods for reducing residual electrons within a NAND string subsequent to performing a sensing operation using the NAND string or during the sensing operation. A middle-out programming sequence may be performed in which memory cell transistors in the middle of the NAND string are programmed and program verified prior to programming and verifying other memory cell transistors towards the drain-side end of the NAND string and/or the source-side end of the NAND string. In one example, for a NAND string with 32 memory cell transistors corresponding with word lines WL0 through WL31 from the source-side end of the NAND string to the drain-side end of the NAND string, the memory cell transistor corresponding with word line WL16 may be programmed and program verified prior to programming the memory cell transistors corresponding with word lines WL15 and WL17.Type: ApplicationFiled: December 20, 2016Publication date: June 22, 2017Applicant: SANDISK TECHNOLOGIES LLCInventors: Xiang Yang, Huai-Yuan Tseng, Xiaochang Miao, Deepanshu Dutta
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Publication number: 20170125117Abstract: Techniques are provided to adaptively determine when to begin verify tests for a particular data state based on a programming progress of a set of memory cells. A count is made in a program-verify iteration of memory cells which pass a verify test of a state N. The count is used to determine a subsequent program-verify iteration in which to perform a verify test of a higher state as a function of an amount by which the count exceeds a threshold count. In another approach, an optimum verify scheme is implemented on a per-group basis for groups of adjacent memory cells at different heights in a 3D memory device. In another approach, an optimum verify scheme is implemented on a per-layer basis for sets of memory cells at a common height or word line layer in a 3D memory device.Type: ApplicationFiled: October 30, 2015Publication date: May 4, 2017Applicant: SANDISK TECHNOLOGIES INC.Inventors: Huai-Yuan Tseng, Deepanshu Dutta, Tai-Yuan Tseng, Grishma Shah, Muhammad Masuduzzaman
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Publication number: 20170125087Abstract: Based on performance during programming, the non-volatile memory cells are classified as fast programming memory cells and slow programming memory cells (or other classifications). At a separate time for each programmed state, threshold voltage distributions are compacted based on the classification.Type: ApplicationFiled: October 29, 2015Publication date: May 4, 2017Applicant: SANDISK TECHNOLOGIES INC.Inventors: Muhammad Masuduzzaman, Tai-Yuan Tseng, Huai-Yuan Tseng, Deepanshu Dutta
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Patent number: 9570179Abstract: Programming non-volatile memory includes applying a series of programming pulses to the memory cells as part of a coarse/fine programming process. Between programming pulses, memory cells in the coarse phase are verified for a coarse phase verify level for a target data state and memory cells in the fine phase are verified for a fine phase verify level for the target data state, both in response to a single reference voltage applied on a common word line. For a memory cell in the coarse phase that has been verified to have reached the coarse phase verify level, the memory cell will be temporarily inhibited from programming for a next programming pulse and switched to the fine phase. For a memory cell in the fine phase that has been verified to have reached the fine phase verify level, the memory cell will be inhibited from further programming.Type: GrantFiled: August 31, 2015Date of Patent: February 14, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Huai-Yuan Tseng, Deepanshu Dutta
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Patent number: 9548130Abstract: A non-volatile memory system comprises a plurality of memory cells arranged in a three dimensional structure and one or more control circuits in communication with the memory cells. The one or more control circuits are configured to program and verify programming for the memory cells. The verifying programming of the plurality of memory cells includes verifying programming for a first data state using a verify operation for a second data state. In one embodiment, the one or more control circuits are also configured to sense whether different memory cells of the plurality of memory cells are in different data states by applying different bit line voltages to the different memory cells.Type: GrantFiled: August 4, 2015Date of Patent: January 17, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Deepanshu Dutta, Huai-Yuan Tseng, Dana Lee, Ken Oowada, Shih-Chung Lee
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Publication number: 20160314843Abstract: Programming non-volatile memory includes applying a series of programming pulses to the memory cells as part of a coarse/fine programming process. Between programming pulses, memory cells in the coarse phase are verified for a coarse phase verify level for a target data state and memory cells in the fine phase are verified for a fine phase verify level for the target data state, both in response to a single reference voltage applied on a common word line. For a memory cell in the coarse phase that has been verified to have reached the coarse phase verify level, the memory cell will be temporarily inhibited from programming for a next programming pulse and switched to the fine phase.Type: ApplicationFiled: August 31, 2015Publication date: October 27, 2016Applicant: SanDisk Technologies Inc.Inventors: Huai-Yuan Tseng, Deepanshu Dutta
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Publication number: 20160314844Abstract: A control circuit, in communication with non-volatile memory cells, is configured to distinguish and classify the memory cells into the different subsets of memory cells based on programming performance. Based on the classifying, the control circuit applies different programming signals to different subsets of the memory cells being programmed to a common data state.Type: ApplicationFiled: October 29, 2015Publication date: October 27, 2016Applicant: SANDISK TECHNOLOGIES INC.Inventors: Deepanshu Dutta, Huai-Yuan Tseng, Farookh Moogat
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Publication number: 20160300620Abstract: A non-volatile memory system comprises a plurality of memory cells arranged in a three dimensional structure and one or more control circuits in communication with the memory cells. The one or more control circuits are configured to program and verify programming for the memory cells. The one or more control circuits are configured to apply a reference voltage to the memory cells. While applying the reference voltage to the plurality of memory cells, the one or more control circuits are configured to sense whether different memory cells of the plurality of memory cells are in different data states by applying different bit line voltages to different bit lines connected to the different memory cells.Type: ApplicationFiled: August 4, 2015Publication date: October 13, 2016Applicant: SANDISK TECHNOLOGIES INC.Inventors: Deepanshu Dutta, Huai-Yuan Tseng, Dana Lee, Ken Oowada, Shih-Chung Lee
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Publication number: 20160300619Abstract: A non-volatile memory system comprises a plurality of memory cells arranged in a three dimensional structure and one or more control circuits in communication with the memory cells. The one or more control circuits are configured to program and verify programming for the memory cells. The verifying programming of the plurality of memory cells includes verifying programming for a first data state using a verify operation for a second data state. In one embodiment, the one or more control circuits are also configured to sense whether different memory cells of the plurality of memory cells are in different data states by applying different bit line voltages to the different memory cells.Type: ApplicationFiled: August 4, 2015Publication date: October 13, 2016Applicant: SANDISK TECHNOLOGIES INC.Inventors: Deepanshu Dutta, Huai-Yuan Tseng, Dana Lee, Ken Oowada, Shih-Chung Lee
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Patent number: 9437321Abstract: Methods for detecting and correcting defects in a memory array during a memory operation are described. The memory operation may comprise a programming operation or an erase operation. In some cases, a Control Gate Short to Substrate (CGSS) defect, in which a control gate of a NAND memory has been shorted to the substrate, may have a defect signature in which a word line shows a deviation in the number of programming loop counts associated with programming data into memory cells connected to the word line. The deviation in the number of programming loop counts may be detected by comparing a baseline programming loop count (e.g., derived from programming a set of one or more word lines prior to programming the word line with the CGSS defect) with a programming loop count associated with programming the word line with the CGSS defect.Type: GrantFiled: October 28, 2014Date of Patent: September 6, 2016Assignee: SANDISK TECHNOLOGIES LLCInventors: Huai-Yuan Tseng, Deepanshu Dutta
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Publication number: 20160217869Abstract: A double lockout programming technique is provided having a hidden delay between programming and verification. A temporary lockout stage and a permanent lockout stage are provided for double lockout programming. The temporary lockout stage precedes the permanent lockout stage and is used to initially determine when a memory cell should be locked out a first time for one or more program pulses. When a memory cell initially passes verification for its target state, it is temporarily locked out from programming for one or more program pulses. The memory cell enters a permanent lockout stage where it is verified again for its target state. When the memory cell passes verification a second time, it is permanently locked out for programming during the current program phase. The memory cell may be programmed at one or more reduced program rates in the permanent lockout stage.Type: ApplicationFiled: October 30, 2015Publication date: July 28, 2016Applicant: SANDISK TECHNOLOGIES INC.Inventors: Huai-Yuan Tseng, Deepanshu Dutta
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Patent number: 9343164Abstract: A method and non-volatile storage system are provided in which the voltage applied to the source end of a NAND string depends on the location of the non-volatile storage element that is selected for sensing. This may be done without body-biasing the NAND string. Having the magnitude of the voltage applied to the source end of a NAND string depend on the location of the selected memory cell (without any body biasing) helps to mitigate failures that are dependent on which word line is selected during a sensing operation of one embodiment. Additionally, the magnitude of a read pass voltage may depend on either the source line voltage or the location of the selected memory cell.Type: GrantFiled: February 18, 2015Date of Patent: May 17, 2016Assignee: SanDisk Technologies Inc.Inventors: Huai-Yuan Tseng, Dana Lee, Shih-Chung Lee, Deepanshu Dutta, Arash Hazeghi