Abstract: Non-volatile memory strings may include multiple selection devices for coupling memory cell devices to a bit line. Different programming operations may be used to program various individual selection devices in a non-volatile memory cells string. For example, a control circuit may set a threshold voltage of a particular selection device to a value greater than a threshold voltage of another selection device. In another example, the control circuit may program the selection device using an initial sense time. Subsequent to programming the selection device using the initial sense time, the control circuit may program the selection device using a different sense time that is shorter than the initial sense time.

Abstract: A circuit includes a program controller configured to perform a program operation with interleaved program-verify loops to program memory cells in a same block. During each program-verify loop, a control gate line voltage supply circuit first supplies a program pulse to a first cell of the block and then, before verifying the first cell, supplies a program pulse to a second cell of the block. After the program pulses are sent, the control gate line supply circuit consecutively supplies verify pulses to the first cell and the second cell such that a delay is introduced between the respective program and verify stages of the first and second cells. Additionally, a constant voltage bias on common control gate lines of the first and second memory cells is applied during the consecutive verify stages. Further, an order of verify pulses may be applied in a reverse order during a verify stage.

Abstract: An apparatus, system, and method are disclosed for identifying and selecting a subgroup of memory cells for use during a programming or erasing operation, in order to execute the programming or erasing operation in less time, while avoiding over and under programming errors. Memory devices disclosed herein may include a state change/programming circuit, a counting circuit, a determination circuit, an identification circuit, and/or a subgroup selection circuit, where each of these circuits are configured to perform operations related to the overall process of identifying and selecting the subgroup of memory cells for utilization during a programming operation.

Abstract: Techniques for fast programming and read operations for memory cells. A first set of bit lines is connected to a first set of NAND strings and is interleaved with a second set of bit lines connected to a second set of NAND strings. The first set of NAND strings can be programmed by driving a voltage on the first set of bit lines while floating a voltage on the second set of bit lines, to reduce an inter-bit line capacitance and provide a relatively high access speed and a relatively low storage density (e.g., bits per memory cell). The second set of NAND strings can be programmed by concurrently driving a voltage on the first and second sets of bit lines, to provide a relatively low access speed and a relatively high storage density.

Abstract: Apparatuses and techniques for fast programming and read operations for memory cells. A group of word lines comprising a selected word line and one or more adjacent word lines are driven with a common voltage signal during program and read operations. The word lines may be permanently connected to one another or connected by a switch. In another approach, the word lines are driven separately by common voltage signals. In a set of blocks, one block of memory cells can be provided with connected word lines to provide a relatively high access speed, while another block of memory cells has disconnected word lines to provide a higher storage density. In another aspect, the memory cells of a word line are divided into portions, and a portion which is closest to a row decoder is reserved for high access speed with a low storage density.

Abstract: An apparatus includes an array of memory cells comprising a first sub-block and a second sub-block electrically coupled by a channel. The apparatus also includes a measurement circuit configured to take a first measurement of a first sub-block of memory cells at a first offset threshold and a second measurement of the first sub-block of memory cells at a second offset threshold. The apparatus further includes a detection circuit configured to detect a disturb condition of the first sub-block based on at least one of the first measurement and the second measurement, and to initiate data maintenance in response to the disturb condition of the first sub-block.

Abstract: Apparatuses, systems, methods, and computer program products for a dynamic bias voltage are presented. A monitor circuit is configured to determine whether an erase loop count of an erase operation for data word lines of an erase block satisfies a threshold. A bias circuit is configured to adjust a voltage applied to one or more dummy word lines of an erase block in response to an erase loop count for data word lines satisfying a threshold. An erase circuit is configured to perform one or more subsequent erase loops of an erase operation for data word lines with an adjusted voltage applied to one or more dummy word lines.

Abstract: Apparatuses and techniques are described for optimizing a program operation in a memory device. A storage location stores programing data for each word line, such as a program voltage for a set of memory cells. The set of memory cells may be periodically evaluated to determine updated programming setting(s). In one approach, the evaluation involves repeatedly sensing the set of memory cells between a program pulse and a verify signal in a program loop. The word line voltage can be stepped down to an intermediate voltage, then ramped down at a controlled rate while repeatedly sensing the memory cells, such as to detect an upper or lower tail of a threshold voltage distribution. The position of the tail can indicate a degree of over programming and this information can be used to adjust the programming setting(s) in a subsequent program operation.

Abstract: Systems and methods reduce device peak current during a read operation by charging control lines of a first set of memory cells faster than control lines of a second set of memory cells while minimizing the channel gradient formed adjacent to a selected word line to suppress occurrences of an injection read disturb in a sense line channel. For example, a first set of memory cells are in a first location relative to a selected memory cell selected for sensing, and a second set of memory cells are in a second location relative to the selected memory cell. The charge device is configured to charge the first set of memory cells and the second set of memory cells. In some aspects, a rate of charging the first set of memory cells is different from a rate of charging the second set of memory cells.

Abstract: Systems and methods reduce device peak current during a read operation by charging control lines of a first set of memory cells faster than control lines of a second set of memory cells while minimizing the channel gradient formed adjacent to a selected word line to suppress occurrences of an injection read disturb in a sense line channel. For example, a first set of memory cells are in a first location relative to a selected memory cell selected for sensing, and a second set of memory cells are in a second location relative to the selected memory cell. The charge device is configured to charge the first set of memory cells and the second set of memory cells. In some aspects, a rate of charging the first set of memory cells is different from a rate of charging the second set of memory cells.

Abstract: Apparatuses and techniques are described for optimizing a program operation in a memory device. A storage location stores programing data for each word line, such as a program voltage for a set of memory cells. The set of memory cells may be periodically evaluated to determine updated programming setting(s). In one approach, the evaluation involves repeatedly sensing the set of memory cells between a program pulse and a verify signal in a program loop. The word line voltage can be stepped down to an intermediate voltage, then ramped down at a controlled rate while repeatedly sensing the memory cells, such as to detect an upper or lower tail of a threshold voltage distribution. The position of the tail can indicate a degree of over programming and this information can be used to adjust the programming setting(s) in a subsequent program operation.

Abstract: An apparatus includes a plurality of solid-state storage elements, a plurality of control lines coupled to the plurality of solid-state storage elements, and control circuitry in communication with the plurality of control lines. The control circuitry is configured to during a first phase of a control line pre-charging stage, charge one or more unselected control lines of the plurality of control lines using a regulated charging current for a period of time based at least in part on a bias variance state associated with the plurality of control lines, and during a second phase of the control line pre-charging stage, charge the one or more unselected bit lines to an inhibit voltage level using an unregulated charging current.

Abstract: A circuit includes a detection circuit configured to determine a capacitance delay (RC-delay) in an initial stage of a read or program operation and to adjust timing for detecting data in a subsequent stage, or portion of a stage, of the same read or programing operation. In particular, during a program operation a detection circuit may be configured to detect a pre-charge time for a bit line and adjust a timing of subsequent verify stages of the bit line during the same program operation based on the detected pre-charge time. Additionally, a word line circuit may be configured to detect a pre-charge time for a word line during an initial stage of a read operation and adjust read timing for a subsequent portion of the same read stage, or subsequent read stage of the read operation based on the detected word line pre-charge time.

Abstract: Apparatuses, systems, and methods are disclosed for adjusting a programming setting such as a programming voltage of a set of non-volatile storage cells, such as an SLC NAND array. The non-volatile storage cells may be arranged into a plurality of word lines. A subset of the non-volatile storage cells may be configured to store a programming setting. An on-die controller may be configured to read the programming setting from the setting subset, and write data to the non-volatile storage cells, using the programming setting. The on-die controller may further be configured to determine that the programming setting causes suboptimal programming of one or more of the non-volatile storage cells, and in response to the determination, store a revised programming setting on the setting subset.

Abstract: A circuit includes selected sense circuits configured to be connected to selected bit lines and unselected sense circuits configured to be connected to unselected bit lines during a sense operation. When the sense circuit is connected to the unselected bit line during the sense operation, the sense circuit is locked out in order to reduce current consumption. However, noise from the locked out sense circuit may be transmitted to the sense circuits connected to the selected bit lines through adjacent bit line coupling. In order to reduce the effect of the noise, charge transfer from the sense node may be blocked from passing to the unselected bit lines. Or, charge may be drained from the sense node, thereby preventing the charge from passing to the unselected bit lines.

Abstract: Disclosed herein is related to a memory device and a method of verifying a programmed status of the memory device. The memory device includes memory cells coupled to a word line. The memory device includes a controller coupled to the word line. The controller is configured to program the memory cells coupled to the word line. The controller is configured to verify a programmed status of a first subset of the memory cells coupled to the word line and a programmed status of a second subset of the memory cells coupled to the word line, based on the programmed status of the first subset of the memory cells.

Abstract: A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation for memory cells in a string. During the erase operation, a channel potential gradient near the select gate transistors is reduced when the voltages of the bit line and the substrate are suitably controlled. In one approach, the voltage of the substrate at a source end of the memory string is increased to an intermediate level first before being increased to the erase voltage threshold level while the voltage of the bit line is held at a reference voltage level to delay floating the voltage of the bit line. Another approach builds off the first approach by temporarily decreasing the voltage of the bit line to a negative level before letting the voltage of the bit line to float at the same time as the voltage of the substrate is increased to the erase voltage threshold level.

Abstract: Apparatuses, systems, methods, and computer program products for a dynamic bias voltage are presented. A monitor circuit is configured to determine whether an erase loop count of an erase operation for data word lines of an erase block satisfies a threshold. A bias circuit is configured to adjust a voltage applied to one or more dummy word lines of an erase block in response to an erase loop count for data word lines satisfying a threshold. An erase circuit is configured to perform one or more subsequent erase loops of an erase operation for data word lines with an adjusted voltage applied to one or more dummy word lines.

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of the memory cells can shift depending on the coupled up state of the word lines. In one approach, for a read operation, a representative word line voltage in a block is detected and a corresponding set of read voltages is selected. In another approach, a pre-read voltage pulse is applied to a selected word line in response to a read command, just prior to reading the selected cells. In another approach, a voltage pulse is periodically applied to each word line in a block to provide the word lines in a coupled up state. In another approach, a soft erase is performed after a read operation to prevent coupling up of the word lines.

Abstract: Systems and methods for reducing residual electrons within a NAND string subsequent to performing a sensing operation using the NAND string or during the sensing operation. A middle-out programming sequence may be performed in which memory cell transistors in the middle of the NAND string are programmed and program verified prior to programming and verifying other memory cell transistors towards the drain-side end of the NAND string and/or the source-side end of the NAND string. In one example, for a NAND string with 32 memory cell transistors corresponding with word lines WL0 through WL31 from the source-side end of the NAND string to the drain-side end of the NAND string, the memory cell transistor corresponding with word line WL16 may be programmed and program verified prior to programming the memory cell transistors corresponding with word lines WL15 and WL17.