Abstract: A linear regulator includes a switching element, an error amplifier circuit, a feedback circuit and a triggering element. A first terminal of the switching element receives an input voltage, and outputs an output voltage to a load through a second terminal. A first input terminal of the error amplifier circuit receives a reference voltage, and an output terminal of the error amplifier circuit is electrically connected to a control terminal of the switching element. The feedback circuit is electrically connected between the second terminal and a second input terminal of the error amplifier circuit. The trigger element is electrically connected to the control terminal and the load to receive a trigger signal. The trigger element outputs a trigger voltage to the control terminal according to the trigger signal, and the switch element is configured to change the output voltage.

Abstract: A comparison control circuit is adapted to analog-to-digital converters and low-dropout regulators. The comparison control circuit includes a comparator, a Schmitt trigger, a capacitor set and a logic circuit. The comparator is configured to output a comparison signal according to a first input signal and a second input signal, wherein the comparison signal is a first high voltage potential or a first low voltage potential. The Schmitt trigger is configured to output a trigger signal according to the comparison signal and a voltage potential range, wherein the voltage potential range is in a range from the first low voltage potential to the first high voltage potential. The capacitor set is configured to adjust the second input signal when being controlled. The logic circuit is configured to control the capacitor set according to the trigger signal to correspondingly adjust the second input signal.

Abstract: A comparator includes an input pair circuit, an isolation circuit, and a latch circuit. The input pair circuit receives first and second input signals to generate first and second signals. The isolation circuit is selectively turned on according to a clock signal to transmit the first signal from the input pair circuit to a first output node and transmit the second signal from the input pair circuit to a second output node. The latch circuit adjusts a level of the first output node to generate a first output signal, adjusts a level of the second output node to generate a second output signal, and selectively resets the levels of the first and the second output nodes according to the clock signal. When the latch circuit resets the levels of the first and the second output nodes, the isolation circuit is not turned on.

Abstract: A sensor placement optimization device is provided, which may include a preprocessing circuit and an operational circuit. The preprocessing circuit may perform a pre-process for the sensing signals of a plurality of temperature sensors, installed on a machine tool, to generate a pre-processed data. The operational circuit may execute a normalization for the pre-processed data to generate a normalized data, perform a principal component analysis for the normalized data to generate a dimensionality-reduced data and implement a principal component regression for the dimensionality-reduced data to obtain the contributions of the temperature sensors. Then, the operational circuit may rank the temperature sensors according to the contributions thereof to generate a ranking result and execute a screening process according to the ranking result to select at least one redundant sensor from the temperature sensors; afterward, the operational circuit may remove the redundant sensor from the temperature sensors.

Abstract: A bootstrapped switch includes a sampling transistor, a bootstrapped circuit, and a buffer circuit. The sampling transistor is configured to be selectively turned on according to a level of a control node, in order to transmit an input signal from a first terminal of the sampling transistor to a second terminal of the sampling transistor, in which a body of the sampling transistor is configured to receive a buffer signal. The bootstrapped circuit is configured to pull up the level of the control node, such that a constant voltage difference is present between the control node and the first terminal of the sampling transistor during a turn-on interval of the sampling transistor. The buffer circuit is configured to generate the buffer signal according to the input signal.

Abstract: A method for outputting a current includes performing a sorting operation on a plurality of current sources according to intensities of currents generated by the current sources, dividing the plurality of current sources into N current source sets according to a result of the sorting operation and a predetermined selection order, and enabling at least one current source set of the N current source sets to output the current according a target output value. The plurality of current sources have a same target current value. Each of the N current source sets includes at least one current source. In the N current source sets, a total quantity of current sources of the nth current source set is twice a total quantity of current sources of the (n?1)th current source set.

Abstract: A comparison control circuit is adapted to analog-to-digital converters and low-dropout regulators. The comparison control circuit includes a comparator, a Schmitt trigger, a capacitor set and a logic circuit. The comparator is configured to output a comparison signal according to a first input signal and a second input signal, wherein the comparison signal is a first high voltage potential or a first low voltage potential. The Schmitt trigger is configured to output a trigger signal according to the comparison signal and a voltage potential range, wherein the voltage potential range is in a range from the first low voltage potential to the first high voltage potential. The capacitor set is configured to adjust the second input signal when being controlled. The logic circuit is configured to control the capacitor set according to the trigger signal to correspondingly adjust the second input signal.

Abstract: Disclosed is a voltage reference buffer circuit including a first, second, third, and fourth bias generators and a first, second, third, and fourth driving components. The first, second, third, and fourth bias generators generate bias voltages to control the first, second, third, and fourth driving components respectively. The first, second, third, and fourth driving components are coupled in sequence, wherein the first and second driving components are different types of transistors and jointly output a first reference voltage, the third and fourth driving components are different types of transistors and jointly output a second reference voltage, and the group of the first and second driving components is separated from the group of the third and fourth driving components by a resistance load.

Abstract: A transmitter device includes a transmitter circuit, a voltage generator circuit, and a calibration circuit. The transmitter circuit is configured to selectively operate in a calibration mode or a normal mode in response to a first control signal, in which the transmitter circuit has a first output terminal and a second output terminal. The voltage generator circuit is configured to generate a bias voltage, in which the bias voltage has a first level in the calibration mode and has a second level in the normal mode, and the first level is different from the second level. The calibration circuit is configured to be turned on in the calibration mode according to the bias voltage and a second control signal, in order to calibrate a level of the first output terminal and a level of the second output terminal.

Abstract: A method for outputting a current includes performing a sorting operation on a plurality of current sources according to intensities of currents generated by the current sources, dividing the plurality of current sources into N current source sets according to a result of the sorting operation and a predetermined selection order, and enabling at least one current source set of the N current source sets to output the current according a target output value. The plurality of current sources have a same target current value. Each of the N current source sets includes at least one current source. In the N current source sets, a total quantity of current sources of the nth current source set is twice a total quantity of current sources of the (n?1)th current source set.

Abstract: Disclosed is a voltage reference buffer circuit including a first, second, third, and fourth bias generators and a first, second, third, and fourth driving components. The first, second, third, and fourth bias generators generate bias voltages to control the first, second, third, and fourth driving components respectively. The first, second, third, and fourth driving components are coupled in sequence, wherein the first and second driving components are different types of transistors and jointly output a first reference voltage, the third and fourth driving components are different types of transistors and jointly output a second reference voltage, and the group of the first and second driving components is separated from the group of the third and fourth driving components by a resistance load.

Abstract: A sensor placement optimization device is provided, which may include a preprocessing circuit and an operational circuit. The preprocessing circuit may perform a pre-process for the sensing signals of a plurality of temperature sensors, installed on a machine tool, to generate a pre-processed data. The operational circuit may execute a normalization for the pre-processed data to generate a normalized data, perform a principal component analysis for the normalized data to generate a dimensionality-reduced data and implement a principal component regression for the dimensionality-reduced data to obtain the contributions of the temperature sensors. Then, the operational circuit may rank the temperature sensors according to the contributions thereof to generate a ranking result and execute a screening process according to the ranking result to select at least one redundant sensor from the temperature sensors; afterward, the operational circuit may remove the redundant sensor from the temperature sensors.

Abstract: A transmitter device includes a transmitter circuit, a voltage generator circuit, and a calibration circuit. The transmitter circuit is configured to selectively operate in a calibration mode or a normal mode in response to a first control signal, in which the transmitter circuit has a first output terminal and a second output terminal. The voltage generator circuit is configured to generate a bias voltage, in which the bias voltage has a first level in the calibration mode and has a second level in the normal mode, and the first level is different from the second level. The calibration circuit is configured to be turned on in the calibration mode according to the bias voltage and a second control signal, in order to calibrate a level of the first output terminal and a level of the second output terminal.

Abstract: A digital-to-analog converter (DAC) device includes a current-steering DAC circuitry and a calibration circuitry. The current-steering DAC circuitry generates a first signal according to multiple least significant bits of an input signal, and generates a second signal according to multiple most significant bits of the input signal. The calibration circuitry performs a non-binary search algorithm to generate a calibration signal in response to a comparison result of the first signal and the second signal, in order to calibrate the current-steering DAC circuitry according to the calibration signal.

Abstract: The present invention provides a voltage difference measurement circuit comprising a level shifting circuit, an ADC and a calculation circuit. In the operations of the voltage difference measurement circuit, the level shifting circuit adjusts levels of a supply voltage and a ground voltage to generate an adjusted supply voltage and an adjusted ground voltage, respectively. The ADC performs an analog-to-digital converting operation upon the adjusted supply voltage and the adjusted ground voltage to generate a first digital value and a second digital value, respectively. The calculation circuit calculates a voltage difference between the supply voltage and the ground voltage according to the first digital value and the second digital value.

Abstract: The present invention provides a voltage difference measurement circuit comprising a level shifting circuit, an ADC and a calculation circuit. In the operations of the voltage difference measurement circuit, the level shifting circuit adjusts levels of a supply voltage and a ground voltage to generate an adjusted supply voltage and an adjusted ground voltage, respectively. The ADC performs an analog-to-digital converting operation upon the adjusted supply voltage and the adjusted ground voltage to generate a first digital value and a second digital value, respectively. The calculation circuit calculates a voltage difference between the supply voltage and the ground voltage according to the first digital value and the second digital value.

Abstract: The present invention discloses an electrostatic discharge (ESD) protection circuit, including: a first terminal configured to receive a first voltage; a second terminal configured to receive a second voltage; a detection voltage generating circuit configured to provide a detection voltage according to the first voltage and the second voltage; a warning circuit configured to generate a control signal according to the detection voltage, in which the control signal indicates a normal condition when the detection voltage satisfies predetermined voltage setting, and the control signal indicates an abnormal condition when the detection voltage does not satisfy the predetermined voltage setting; and a protected circuit configured to carry out a self-protection operation when receiving the control signal indicating the abnormal condition.

Abstract: A digital-to-analog converter (DAC) device includes a current-steering DAC circuitry and a calibration circuitry. The current-steering DAC circuitry generates a first signal according to multiple least significant bits of an input signal, and generates a second signal according to multiple most significant bits of the input signal. The calibration circuitry performs a non-binary search algorithm to generate a calibration signal in response to a comparison result of the first signal and the second signal, in order to calibrate the current-steering DAC circuitry according to the calibration signal.

Abstract: A charge-pump boosting is provided. A first resistor is connected to a first storage capacitor and receives a reference voltage, and a second resistor is connected to a second storage capacitor and receives the reference voltage. A first rectifying device is connected to the first storage capacitor and a voltage output. A first clock signal and the reference voltage are used to charge the first storage capacitor, and the first clock signal is used to selectively turn on the first rectifying device to charge the voltage output by the first storage capacitor. The second rectifying device is connected to the second storage capacitor and the voltage output. A second clock signal and the reference voltage are used to charge the second storage capacitor, and the second clock signal is used to selectively turn on the second rectifying device to charge the voltage output by the second storage capacitor.

Abstract: A charge-pump boosting is provided. A first resistor is connected to a first storage capacitor and receives a reference voltage, and a second resistor is connected to a second storage capacitor and receives the reference voltage. A first rectifying device is connected to the first storage capacitor and a voltage output. A first clock signal and the reference voltage are used to charge the first storage capacitor, and the first clock signal is used to selectively turn on the first rectifying device to charge the voltage output by the first storage capacitor. The second rectifying device is connected to the second storage capacitor and the voltage output. A second clock signal and the reference voltage are used to charge the second storage capacitor, and the second clock signal is used to selectively turn on the second rectifying device to charge the voltage output by the second storage capacitor.