Patents by Inventor Huan Lei

Huan Lei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200403501
    Abstract: A charge-pump boosting is provided. A first resistor is connected to a first storage capacitor and receives a reference voltage, and a second resistor is connected to a second storage capacitor and receives the reference voltage. A first rectifying device is connected to the first storage capacitor and a voltage output. A first clock signal and the reference voltage are used to charge the first storage capacitor, and the first clock signal is used to selectively turn on the first rectifying device to charge the voltage output by the first storage capacitor. The second rectifying device is connected to the second storage capacitor and the voltage output. A second clock signal and the reference voltage are used to charge the second storage capacitor, and the second clock signal is used to selectively turn on the second rectifying device to charge the voltage output by the second storage capacitor.
    Type: Application
    Filed: September 24, 2019
    Publication date: December 24, 2020
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Chien-Ming Wu, Shih-Hsiung Huang, Liang-Huan Lei
  • Patent number: 10873256
    Abstract: A charge-pump boosting is provided. A first resistor is connected to a first storage capacitor and receives a reference voltage, and a second resistor is connected to a second storage capacitor and receives the reference voltage. A first rectifying device is connected to the first storage capacitor and a voltage output. A first clock signal and the reference voltage are used to charge the first storage capacitor, and the first clock signal is used to selectively turn on the first rectifying device to charge the voltage output by the first storage capacitor. The second rectifying device is connected to the second storage capacitor and the voltage output. A second clock signal and the reference voltage are used to charge the second storage capacitor, and the second clock signal is used to selectively turn on the second rectifying device to charge the voltage output by the second storage capacitor.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: December 22, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Chien-Ming Wu, Shih-Hsiung Huang, Liang-Huan Lei
  • Patent number: 10729117
    Abstract: The present invention relates to a pest monitoring method based on machine vision. The method includes the following steps: arranging a pest trap at a place where pests gather, and setting an image acquisition device in front of the pest trap to acquire an image; identifying a pest in the acquired image, and obtaining a number of pests; extracting multiple suspicious pest images from a region of each identified pest in the image, and determining identification accuracy of each suspicious pest image, if the number of pests is greater than or equal to a preset threshold for the number of pests; and calculating a predicted level of pest damage based on the number of pests and the identification accuracy of each suspicious pest image. The present invention acquires a pest image automatically through the image acquisition device in front of the pest trap.
    Type: Grant
    Filed: December 25, 2017
    Date of Patent: August 4, 2020
    Assignee: ZHONGKAI UNIVERSITY OF AGRICULTURE AND ENGINEER
    Inventors: Yu Tang, Shaoming Luo, Zhenyu Zhong, Huan Lei, Chaojun Hou, Jiajun Zhuang, Weifeng Huang, Zaili Chen, Jintian Lin, Lixue Zhu
  • Patent number: 10693487
    Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) and a method of operating the SAR ADC are provided. The SAR ADC converts an analog input signal into a digital code and includes a switch-capacitor digital-to-analog converter (DAC), and the switch-capacitor DAC includes multiple capacitors. The method includes the steps of: switching terminal voltage(s) of at least one target capacitor among the capacitors according to a data in a sampling phase; sampling the analog input signal in the sampling phase; switching the terminal voltage(s) of the at least one target capacitor after the sampling phase; comparing the outputs of the switch-capacitor DAC to obtain multiple comparison results that constitute the digital code; and switching the terminal voltages of a part of the capacitors according to the comparison results.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: June 23, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Liang-Huan Lei, Shih-Hsiung Huang
  • Publication number: 20200195269
    Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) and a method of operating the SAR ADC are provided. The SAR ADC converts an analog input signal into a digital code and includes a switch-capacitor digital-to-analog converter (DAC), and the switch-capacitor DAC includes multiple capacitors. The method includes the steps of: switching terminal voltage(s) of at least one target capacitor among the capacitors according to a data in a sampling phase; sampling the analog input signal in the sampling phase; switching the terminal voltage(s) of the at least one target capacitor after the sampling phase; comparing the outputs of the switch-capacitor DAC to obtain multiple comparison results that constitute the digital code; and switching the terminal voltages of a part of the capacitors according to the comparison results.
    Type: Application
    Filed: September 18, 2019
    Publication date: June 18, 2020
    Inventors: LIANG-HUAN LEI, SHIH-HSIUNG HUANG
  • Publication number: 20200178511
    Abstract: The present invention relates to a pest monitoring method based on machine vision. The method includes the following steps: arranging a pest trap at a place where pests gather, and setting an image acquisition device in front of the pest trap to acquire an image; identifying a pest in the acquired image, and obtaining a number of pests; extracting multiple suspicious pest images from a region of each identified pest in the image, and determining identification accuracy of each suspicious pest image, if the number of pests is greater than or equal to a preset threshold for the number of pests; and calculating a predicted level of pest damage based on the number of pests and the identification accuracy of each suspicious pest image. The present invention acquires a pest image automatically through the image acquisition device in front of the pest trap.
    Type: Application
    Filed: December 25, 2017
    Publication date: June 11, 2020
    Inventors: Yu TANG, Shaoming LUO, Zhenyu ZHONG, Huan LEI, Chaojun HOU, Jiajun ZHUANG, Weifeng HUANG, Zaili CHEN, Jintian LIN, Lixue ZHU
  • Patent number: 10615814
    Abstract: The present invention discloses a pipelined analog-to-digital converter (ADC) including a sub-ADC, a multiplying digital-to-analog converter (MDAC) and a decoder. The decoder provides a ground signal for the MDAC. The sub-ADC is electrically connected to a ground pad via a first metal trace, and the decoder is electrically connected to the ground pad via a second metal trace.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: April 7, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chien-Ming Wu, Liang-Huan Lei, Shih-Hsiung Huang
  • Publication number: 20200106452
    Abstract: A digital-to-analog converter (DAC) device includes a DAC circuitry and a calibration circuitry. The DAC circuitry generates a first signal according to least significant bits of an input signal, and generates a second signal according to most significant bits of the input signal. The calibration circuitry compares the first signal with the second signal to generate a calibration signal, and calibrates the DAC circuitry according to the calibration signal. The calibration signal has bits. The calibration circuitry further repeatedly compares the first signal and the second signal to generate a plurality of comparison results when determining at least one bit of the bits, and performs a statistic operation according to the comparison results, in order to adjust the at least one bit, and a number of the at least one bit is less than a number of the bits.
    Type: Application
    Filed: April 16, 2019
    Publication date: April 2, 2020
    Inventors: Chih-Chieh Yang, Shih-Hsiung Huang, Liang-Huan Lei
  • Patent number: 10598726
    Abstract: A self-test circuit and a self-test method for a comparator are provided. A first output terminal of the comparator is coupled to an input terminal of a first inverter, and a second output terminal of the comparator is coupled to an input terminal of a second inverter. The comparator operates in a reset phase or a comparison phase according to a clock. The self-test method includes steps of: coupling the first output terminal and the second output terminal so that the comparator enters a test mode; and in the test mode, controlling the comparator to operate in the reset phase or the comparison phase according to the clock. In the test mode, the first output terminal and the second output terminal have substantially the same voltage.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: March 24, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Liang-Huan Lei, Shih-Hsiung Huang, Chih-Lung Chen
  • Publication number: 20200091924
    Abstract: The present invention discloses a pipelined analog-to-digital converter (ADC) including a sub-ADC, a multiplying digital-to-analog converter (MDAC) and a decoder. The decoder provides a ground signal for the MDAC. The sub-ADC is electrically connected to a ground pad via a first metal trace, and the decoder is electrically connected to the ground pad via a second metal trace.
    Type: Application
    Filed: May 31, 2019
    Publication date: March 19, 2020
    Inventors: CHIEN-MING WU, LIANG-HUAN LEI, SHIH-HSIUNG HUANG
  • Patent number: 10594332
    Abstract: A front-end receiving circuit includes a first input terminal receiving a first signal, a second input terminal receiving a second signal, a comparator, a first sampling switch, a first sampling shifting circuit and a control circuit. The first sampling switch is coupled between the first input terminal and the first comparator input terminal. The first sample shifting circuit includes a first capacitor, a first reference voltage source, and a second reference voltage source. In a sampling mode, the control circuit is configured to control the first sampling switch and the second sampling switch to be turned on, and control the first shifting switch to be turned off. In a shifting mode, the control circuit is configured to control the first sampling switch and the second sampling to be turned off, and control the first shifting switch to be turned on.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: March 17, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Liang-Huan Lei, Jian-Ru Lin, Shih-Hsiung Huang
  • Patent number: 10587279
    Abstract: A digital-to-analog converter (DAC) device includes a DAC circuitry and a calibration circuitry. The DAC circuitry generates a first signal according to least significant bits of an input signal, and generates a second signal according to most significant bits of the input signal. The calibration circuitry compares the first signal with the second signal to generate a calibration signal, and calibrates the DAC circuitry according to the calibration signal. The calibration signal has bits. The calibration circuitry further repeatedly compares the first signal and the second signal to generate a plurality of comparison results when determining at least one bit of the bits, and performs a statistic operation according to the comparison results, in order to adjust the at least one bit, and a number of the at least one bit is less than a number of the bits.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: March 10, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chih-Chieh Yang, Shih-Hsiung Huang, Liang-Huan Lei
  • Publication number: 20200044639
    Abstract: A latch circuit includes a switch circuit, an input circuit, and an output circuit. The switch circuit is coupled between a first power node and a second power node, and includes a non-inverting output node and an inverting output node. The input circuit couples with the non-inverting output node and the inverting output node, and conducts the non-inverting output node with the second power node according to a clock signal and a data signal. The output circuit couples with the non-inverting output node, the inverting output node, the first power node, and the second power node. The output circuit conducts the non-inverting output node with the first power node according to the clock signal and the data signal. When the data signal is switched, the switch circuit sets a conductive path from the first power node to the second power node as an open circuit.
    Type: Application
    Filed: July 23, 2019
    Publication date: February 6, 2020
    Inventors: Jian-Ru LIN, Liang-Huan LEI
  • Publication number: 20200014394
    Abstract: A front-end receiving circuit includes a first input terminal receiving a first signal, a second input terminal receiving a second signal, a comparator, a first sampling switch, a first sampling shifting circuit and a control circuit. The first sampling switch is coupled between the first input terminal and the first comparator input terminal. The first sample shifting circuit includes a first capacitor, a first reference voltage source, and a second reference voltage source. In a sampling mode, the control circuit is configured to control the first sampling switch and the second sampling switch to be turned on, and control the first shifting switch to be turned off. In a shifting mode, the control circuit is configured to control the first sampling switch and the second sampling to be turned off, and control the first shifting switch to be turned on.
    Type: Application
    Filed: April 29, 2019
    Publication date: January 9, 2020
    Inventors: LIANG-HUAN LEI, JIAN-RU LIN, SHIH-HSIUNG HUANG
  • Patent number: 10530358
    Abstract: A switching circuit includes: a main switch array including multiple main switch elements respectively arranged on multiple main signal paths configured in a parallel connection, wherein the multiple main signal paths are coupled with a first circuit node; a main switch control circuit for controlling the multiple main switch elements; an auxiliary switch array including multiple auxiliary switch elements respectively arranged on multiple auxiliary signal paths configured in a parallel connection, wherein the multiple auxiliary signal paths are also coupled with the first circuit node; and an auxiliary switch control circuit for controlling the multiple auxiliary switch elements so as to maintain a total number of turned-on switch elements in the main switch array and the auxiliary switch array to be equal to or more than a threshold quantity.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: January 7, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Cheng-Pang Chan, Liang-Huan Lei
  • Patent number: 10498349
    Abstract: Disclosed is a bit error rate (BER) forecast circuit for successive approximation register analog-to-digital conversion. The BER forecast circuit includes an N bits successive approximation register analog-to-digital converter (N bits SAR ADC) and an estimation circuit. The N bits SAR ADC is configured to carry out a regular operation at least N times and an additional operation at least X time(s) in one cycle of conversion time, in which the N is an integer greater than 1 and the X is an integer not less than zero. The estimation circuit is configured to generate a test value according to total times the N bits SAR ADC carrying out the additional operation in Y cycles of the conversion time, in which the Y is a positive integer and the test value is related to the bit error rate of the N bits SAR ADC.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: December 3, 2019
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yu-Xuan Huang, Liang-Huan Lei, Shih-Hsiung Huang, Liang-Wei Huang
  • Patent number: 10396725
    Abstract: An amplifier includes an output stage circuit and a compensation circuit. The output stage circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The compensation circuit includes a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. The first capacitor is coupled between the first input terminal and the second output terminal, and is configured to operate as a first Miller capacitor. The second capacitor is coupled between the second input terminal and the first output terminal, and is configured to operate as a second Miller capacitor. The third capacitor and the fourth capacitor are configured to alternately operate as the first Miller capacitor and the second Miller capacitor according to at least one clock signal.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: August 27, 2019
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chien-Ming Wu, Liang-Huan Lei, Shih-Hsiung Huang, Chih-Lung Chen
  • Publication number: 20190204385
    Abstract: A self-test circuit and a self-test method for a comparator are provided. A first output terminal of the comparator is coupled to an input terminal of a first inverter, and a second output terminal of the comparator is coupled to an input terminal of a second inverter. The comparator operates in a reset phase or a comparison phase according to a clock. The self-test method includes steps of: coupling the first output terminal and the second output terminal so that the comparator enters a test mode; and in the test mode, controlling the comparator to operate in the reset phase or the comparison phase according to the clock. In the test mode, the first output terminal and the second output terminal have substantially the same voltage.
    Type: Application
    Filed: September 20, 2018
    Publication date: July 4, 2019
    Inventors: LIANG-HUAN LEI, SHIH-HSIUNG HUANG, CHIH-LUNG CHEN
  • Publication number: 20190140654
    Abstract: Disclosed is a bit error rate (BER) forecast circuit for successive approximation register analog-to-digital conversion. The BER forecast circuit includes an N bits successive approximation register analog-to-digital converter (N bits SAR ADC) and an estimation circuit. The N bits SAR ADC is configured to carry out a regular operation at least N times and an additional operation at least X time(s) in one cycle of conversion time, in which the N is an integer greater than 1 and the X is an integer not less than zero. The estimation circuit is configured to generate a test value according to total times the N bits SAR ADC carrying out the additional operation in Y cycles of the conversion time, in which the Y is a positive integer and the test value is related to the bit error rate of the N bits SAR ADC.
    Type: Application
    Filed: October 23, 2018
    Publication date: May 9, 2019
    Inventors: YU-XUAN HUANG, LIANG-HUAN LEI, SHIH-HSIUNG HUANG, LIANG-WEI HUANG
  • Publication number: 20190074800
    Abstract: An amplifier includes an output stage circuit and a compensation circuit. The output stage circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The compensation circuit includes a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. The first capacitor is coupled between the first input terminal and the second output terminal, and is configured to operate as a first Miller capacitor. The second capacitor is coupled between the second input terminal and the first output terminal, and is configured to operate as a second Miller capacitor. The third capacitor and the fourth capacitor are configured to alternately operate as the first Miller capacitor and the second Miller capacitor according to at least one clock signal.
    Type: Application
    Filed: January 10, 2018
    Publication date: March 7, 2019
    Inventors: Chien-Ming WU, Liang-Huan LEI, Shih-Hsiung HUANG, Chih-Lung CHEN