Abstract: A circuit includes an operational amplifier configured to output a driving signal according to a feedback voltage associated with an output voltage and a reference voltage, a pass gate circuit comprising switches in current paths, and hysteresis comparators connected to the operational amplifier and configured to generate control signals to separately turn on or off the switches in the current paths in response to the driving signal.

Abstract: A semiconductor device includes: a magnetic core; a conductive coil winding around the magnetic core and electrically insulated from the magnetic core, wherein the conductive coil includes horizontally-extending conductive lines and vertically-extending conductive vias electrically connecting the horizontally-extending conductive lines; and a connecting metal line on an outside of and electrically isolated from the conductive coil. The vertically-extending conductive vias include first conductive vias overlying a first one of the horizontally-extending conductive lines, second conductive vias overlapping the first conductive vias and underlying a second one of the horizontally-extending conductive lines, and a third conductive via between the first conductive vias and the second conductive vias. The connecting metal line is between the first conductive vias and the second conductive vias from a cross-sectional view.

Abstract: Disclosed is a system and method for communication using an efficient fiber-to-chip grating coupler with a high coupling efficiency.

Abstract: In an embodiment, a circuit includes: a transformer defining an inductive footprint within a first layer; a grounded shield bounded by the inductive footprint within a second layer separate from the first layer; and a circuit component bounded by the inductive footprint within a third layer separate from the second layer, wherein: the circuit component is coupled with the transformer through the second layer, and the third layer is separated from the first layer by the second layer.

Abstract: A semiconductor structure according to the present disclosure includes a buried oxide layer, a first dielectric layer disposed over the buried oxide layer, a first waveguide feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first waveguide feature, a third dielectric layer disposed over the second dielectric layer, and a second waveguide feature disposed in the second dielectric layer and the third dielectric layer. The second waveguide feature is disposed over the first waveguide feature and a portion of the second waveguide feature vertically overlaps a portion of the first waveguide feature.

Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.

Abstract: A method includes: forming an interconnect structure over a semiconductor substrate. The interconnect structure includes: a magnetic core and a conductive coil winding around the magnetic core and electrically insulated from the magnetic core. The conductive coil includes horizontally-extending conductive lines and vertically-extending conductive vias electrically connecting the horizontally-extending conductive lines, wherein the magnetic core and the conductive coil are arranged in an inductor zone of the interconnect structure; and a connecting metal line adjacent to and on an outside of the inductor zone, the connecting metal line being electrical isolated from the inductor zone. The vertically-extending conductive vias include first conductive vias, second conductive vias, and a third conductive via between the first conductive vias and the second conductive vias.

Abstract: Disclosed is a system and method for communication using an efficient fiber-to-chip grating coupler with a high coupling efficiency.

Abstract: An optical device includes a waveguide configured to guide light, a taper integrated with the waveguide on a substrate configured for optical coupling, and an attenuator to degrade unwanted optical signal from the taper. The attenuator extends along one side of the taper, and includes one of a conductive structure, a doped structure and a refractive structure.

Abstract: A built-in self-tester (BIST) of a semiconductor device including: an input/output (I/O) circuit including an output buffer and an input buffer, an output of the output buffer being coupled at an I/O terminal to an input of the input buffer, the I/O terminal being configured to receive or provide an external I/O signal; one or more resistive-network cell regions arranged to affect a reference current received at the I/O terminal; and a switching arrangement configured to selectively couple the one or more resistive-network cell regions alternatively to a first reference voltage during a first phase or a second reference voltage during a second phase, the switching arrangement being further configured to determine electrostatic discharge (ESD) damage to metal-oxide-semiconductor (MOS) transistors included in the semiconductor device based on (1) phase and (2) an output signal of the input buffer

Abstract: A method includes etching a silicon layer to form a silicon slab and an upper silicon region over the silicon slab, and implanting the silicon slab and the upper silicon region to form a p-type region, an n-type region, and an intrinsic region between the p-type region and the n-type region. The method further includes etching the p-type region, the n-type region, and the intrinsic region to form a trench. The remaining portions of the upper silicon region form a Multi-Mode Interferometer (MMI) region. An epitaxy process is performed to grow a germanium region in the trench. Electrical connections are made to connect to the p-type region and the n-type region.

Abstract: Systems and methods are provided for an integrated chip. An integrated chip includes a package substrate including a plurality of first layers and a plurality of second layers, each second layer being disposed between a respective adjacent pair of the first layers. A transceiver unit is disposed above the package substrate. A waveguide unit including a plurality of waveguides having top and bottom walls formed in the first layers of the package substrate and sidewalls formed in the second layers of the package substrate.

Abstract: An optical device includes a waveguide configured to guide light, a taper integrated with the waveguide on a substrate configured for optical coupling, and an attenuator to degrade unwanted optical signal from the taper. The attenuator extends along one side of the taper, and includes one of a conductive structure, a doped structure and a refractive structure.

Abstract: An optical modulator includes a waveguide. The waveguide includes a first optical coupling region, a first electrical coupling region, and a first plurality of regions. The first optical coupling region is doped with first dopants. The first electrical coupling region is doped with the first dopants. The first plurality of regions are doped with the first dopants and are sandwiched between the first optical coupling region and the first electrical coupling region. The first plurality of regions have respective decreasing doping concentrations as distances of the first plurality of regions increase from the first electrical coupling region. The first plurality of regions have respective decreasing heights as the distances of the first plurality of regions increase from the first electrical coupling region. A maximum doping concentration of the first plurality of regions is smaller than a doping concentration of the first electrical coupling region.

Abstract: A method includes etching a silicon layer to form a silicon slab and an upper silicon region over the silicon slab, and implanting the silicon slab and the upper silicon region to form a p-type region, an n-type region, and an intrinsic region between the p-type region and the n-type region. The method further includes etching the p-type region, the n-type region, and the intrinsic region to form a trench. The remaining portions of the upper silicon region form a Multi-Mode Interferometer (MMI) region. An epitaxy process is performed to grow a germanium region in the trench. Electrical connections are made to connect to the p-type region and the n-type region.

Abstract: The present disclosure provides a crack detection unit (CDU), a semiconductor die, and a method of detecting a crack of a semiconductor die. The CDU comprises a switching circuit, a crack sensor, and a logic circuit. The switching circuit is configured to enable the crack sensor. The crack sensor is configured to be electrically connected to the switching circuit, the ground, and an operating voltage. The logic circuit is configured to be electrically connected to the switching circuit and the crack sensor, wherein the CDU is enabled based on an input of the logic circuit. The output of the logic circuit indicates whether the crack sensor contains a crack.

Abstract: A semiconductor package includes a first semiconductor device, a second semiconductor device vertically positioned above the first semiconductor device, and a ground shielded transmission path. The ground shielded transmission path couples the first semiconductor device to the second semiconductor device. The ground shielded transmission path includes a first signal path extending longitudinally between a first end and a second end. The first signal path includes a conductive material. A first insulating layer is disposed over the signal path longitudinally between the first end and the second end. The first insulating layer includes an electrically insulating material. A ground shielding layer is disposed over the insulating material longitudinally between the first end and the second end of the signal path. The ground shielding layer includes a conductive material coupled to ground.

Abstract: An optical modulator includes a carrier and a waveguide disposed on the carrier. The waveguide includes a first optical coupling region, a second optical coupling region, first regions, and second regions. The first optical coupling region is doped with first dopants. The second optical coupling region abuts the first optical coupling region and is doped with second dopants. The first dopants and the second dopants are of different conductivity type. The first regions are doped with the first dopants and are arrange adjacent to the first optical coupling region. The first regions have respective increasing doping concentrations as distances of the first regions increase from the first optical coupling region. The second regions are doped with the second dopants and are arranged adjacent to the second optical coupling region. The second regions have respective increasing doping concentrations as distances of the second regions increase from the second optical coupling region.

Abstract: A device includes a scattering structure and a collection structure. The scattering structure is arranged to concurrently scatter incident electromagnetic radiation along a first scattering axis and along a second scattering axis. The first scattering axis and the second scattering axis are non-orthogonal. The collection structure includes a first input port aligned with the first scattering axis and a second input port aligned with the second scattering axis. A method includes scattering electromagnetic radiation along a first scattering axis to create first scattered electromagnetic radiation and along a second scattering axis to create second scattered electromagnetic radiation. The first scattering axis and the second scattering axis are non-orthogonal. The first scattered electromagnetic radiation is detected to yield first detected radiation and the second scattered electromagnetic radiation is detected to yield second detected radiation.

Abstract: The present disclosure provides a crack detection unit (CDU), a semiconductor die, and a method of detecting a crack of a semiconductor die. The CDU comprises a switching circuit, a crack sensor, and a logic circuit. The switching circuit is configured to enable the crack sensor. The crack sensor is configured to be electrically connected to the switching circuit, the ground, and an operating voltage. The logic circuit is configured to be electrically connected to the switching circuit and the crack sensor, wherein the CDU is enabled based on an input of the logic circuit. The output of the logic circuit indicates whether the crack sensor contains a crack.