Patents by Inventor Huan-Neng CHEN

Huan-Neng CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12140800
    Abstract: A method includes etching a silicon layer to form a silicon slab and an upper silicon region over the silicon slab, and implanting the silicon slab and the upper silicon region to form a p-type region, an n-type region, and an intrinsic region between the p-type region and the n-type region. The method further includes etching the p-type region, the n-type region, and the intrinsic region to form a trench. The remaining portions of the upper silicon region form a Multi-Mode Interferometer (MMI) region. An epitaxy process is performed to grow a germanium region in the trench. Electrical connections are made to connect to the p-type region and the n-type region.
    Type: Grant
    Filed: June 24, 2022
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Weiwei Song, Stefan Rusu, Chewn-Pu Jou, Huan-Neng Chen
  • Publication number: 20240369613
    Abstract: The present disclosure provides a crack detection unit (CDU), a semiconductor die, and a method of detecting a crack of a semiconductor die. The CDU comprises a switching circuit, a crack sensor, and a logic circuit. The switching circuit is configured to enable the crack sensor. The crack sensor is configured to be electrically connected to the switching circuit, the ground, and an operating voltage. The logic circuit is configured to be electrically connected to the switching circuit and the crack sensor, wherein the CDU is enabled based on an input of the logic circuit. The output of the logic circuit indicates whether the crack sensor contains a crack.
    Type: Application
    Filed: July 16, 2024
    Publication date: November 7, 2024
    Inventors: HUAN-NENG CHEN, SHAO-YU LI
  • Publication number: 20240363560
    Abstract: A semiconductor package includes a first semiconductor device, a second semiconductor device vertically positioned above the first semiconductor device, and a ground shielded transmission path. The ground shielded transmission path couples the first semiconductor device to the second semiconductor device. The ground shielded transmission path includes a first signal path extending longitudinally between a first end and a second end. The first signal path includes a conductive material. A first insulating layer is disposed over the signal path longitudinally between the first end and the second end. The first insulating layer includes an electrically insulating material. A ground shielding layer is disposed over the insulating material longitudinally between the first end and the second end of the signal path. The ground shielding layer includes a conductive material coupled to ground.
    Type: Application
    Filed: July 8, 2024
    Publication date: October 31, 2024
    Inventors: Feng Wei KUO, Wen-Shiang LIAO, Chewn-Pu JOU, Huan-Neng CHEN, Lan-Chou CHO, William Wu SHEN
  • Patent number: 12124119
    Abstract: An optical modulator includes a carrier and a waveguide disposed on the carrier. The waveguide includes a first optical coupling region, a second optical coupling region, first regions, and second regions. The first optical coupling region is doped with first dopants. The second optical coupling region abuts the first optical coupling region and is doped with second dopants. The first dopants and the second dopants are of different conductivity type. The first regions are doped with the first dopants and are arrange adjacent to the first optical coupling region. The first regions have respective increasing doping concentrations as distances of the first regions increase from the first optical coupling region. The second regions are doped with the second dopants and are arranged adjacent to the second optical coupling region. The second regions have respective increasing doping concentrations as distances of the second regions increase from the second optical coupling region.
    Type: Grant
    Filed: February 8, 2023
    Date of Patent: October 22, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lan-Chou Cho, Chewn-Pu Jou, Feng-Wei Kuo, Huan-Neng Chen, Min-Hsiang Hsu
  • Publication number: 20240337528
    Abstract: A device includes a scattering structure and a collection structure. The scattering structure is arranged to concurrently scatter incident electromagnetic radiation along a first scattering axis and along a second scattering axis. The first scattering axis and the second scattering axis are non-orthogonal. The collection structure includes a first input port aligned with the first scattering axis and a second input port aligned with the second scattering axis. A method includes scattering electromagnetic radiation along a first scattering axis to create first scattered electromagnetic radiation and along a second scattering axis to create second scattered electromagnetic radiation. The first scattering axis and the second scattering axis are non-orthogonal. The first scattered electromagnetic radiation is detected to yield first detected radiation and the second scattered electromagnetic radiation is detected to yield second detected radiation.
    Type: Application
    Filed: June 20, 2024
    Publication date: October 10, 2024
    Inventors: Chewn-Pu JOU, Feng Wei KUO, Huan-Neng CHEN, Lan-Chou CHO
  • Patent number: 12111346
    Abstract: The present disclosure provides a crack detection unit (CDU), a semiconductor die, and a method of detecting a crack of a semiconductor die. The CDU comprises a switching circuit, a crack sensor, and a logic circuit. The switching circuit is configured to enable the crack sensor. The crack sensor is configured to be electrically connected to the switching circuit, the ground, and an operating voltage. The logic circuit is configured to be electrically connected to the switching circuit and the crack sensor, wherein the CDU is enabled based on an input of the logic circuit. The output of the logic circuit indicates whether the crack sensor contains a crack.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: October 8, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Huan-Neng Chen, Shao-Yu Li
  • Publication number: 20240329304
    Abstract: An optical attenuating structure is provided. The optical attenuating structure includes a substrate, a waveguide, doping regions, an optical attenuating member, and a dielectric layer. The waveguide is extended over the substrate. The doping regions are disposed over the substrate, and include a first doping region, a second doping region opposite to the first doping region and separated from the first doping region by the waveguide, a first electrode extended over the substrate and in the first doping region, and a second electrode extended over the substrate and in the second doping region. The first optical attenuating member is coupled with the waveguide and disposed between the waveguide and the first electrode. The dielectric layer is disposed over the substrate and covers the waveguide, the doping regions and the first optical attenuating member.
    Type: Application
    Filed: March 29, 2023
    Publication date: October 3, 2024
    Inventors: HUAN-NENG CHEN, FENG-WEI KUO, MIN-HSIANG HSU, LAN-CHOU CHO, CHEWN-PU JOU, WEN-SHIANG LIAO
  • Patent number: 12095711
    Abstract: An integrated circuit includes first through fourth devices positioned over one or more substrates, a first radio frequency interconnect (RFI) including a first transmitter included in the first device, a first receiver included in the second device, and a first guided transmission medium coupled to each of the first transmitter and the first receiver, a second RFI including a second transmitter included in the first device, a second receiver included in the third device, and a second guided transmission medium coupled to each of the second transmitter and the second receiver, and a third RFI including a third transmitter included in the first device, a third receiver included in the fourth device, and the second guided transmission medium coupled to each of the third transmitter and the third receiver.
    Type: Grant
    Filed: March 27, 2023
    Date of Patent: September 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huan-Neng Chen, William Wu Shen, Chewn-Pu Jou, Feng Wei Kuo, Lan-Chou Cho, Tze-Chiang Huang, Jack Liu, Yun-Han Lee
  • Patent number: 12074125
    Abstract: A semiconductor package includes a first semiconductor device, a second semiconductor device vertically positioned above the first semiconductor device, and a ground shielded transmission path. The ground shielded transmission path couples the first semiconductor device to the second semiconductor device. The ground shielded transmission path includes a first signal path extending longitudinally between a first end and a second end. The first signal path includes a conductive material. A first insulating layer is disposed over the signal path longitudinally between the first end and the second end. The first insulating layer includes an electrically insulating material. A ground shielding layer is disposed over the insulating material longitudinally between the first end and the second end of the signal path. The ground shielding layer includes a conductive material coupled to ground.
    Type: Grant
    Filed: March 21, 2023
    Date of Patent: August 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng Wei Kuo, Wen-Shiang Liao, Chewn-Pu Jou, Huan-Neng Chen, Lan-Chou Cho, William Wu Shen
  • Patent number: 12062629
    Abstract: Systems and methods are provided for an integrated chip. An integrated chip includes a package substrate including a plurality of first layers and a plurality of second layers, each second layer being disposed between a respective adjacent pair of the first layers. A transceiver unit is disposed above the package substrate. A waveguide unit including a plurality of waveguides having top and bottom walls formed in the first layers of the package substrate and sidewalls formed in the second layers of the package substrate.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: August 13, 2024
    Assignees: Taiwan Semiconductor Manufacturing Company Limited, The University of California, Los Angeles (UCLA)
    Inventors: Huan-Neng Chen, Chewn-Pu Jou, Feng Wei Kuo, Lan-Chou Cho, Wen-Shiang Liao, Yanghyo Kim
  • Publication number: 20240255977
    Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.
    Type: Application
    Filed: April 11, 2024
    Publication date: August 1, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Neng CHEN, Yen-Lin LIU, Chia-Wei HSU, Jo-Yu WU, CHANG-FEN HU, Shao-Yu LI, Bo-Ting CHEN
  • Publication number: 20240259004
    Abstract: In some embodiments, digital logic components, such as those found in standard cells in integrated circuit devices, are used to synthesize signals with controllable waveforms that result in transmitted signals that meet certain requirements, such as above-threshold high openings and below-threshold over/under-shooting. In some embodiments, driving buffers with logic controls and delay chains are used to achieve controllable slew rates at rising and falling edges to minimize over/under shooting behavior in signals. In some embodiments, control logic and delay chains produce controllable rising/falling “stair-type” edges to obtain optimized damping waveform.
    Type: Application
    Filed: April 11, 2024
    Publication date: August 1, 2024
    Inventors: Huan-Neng CHEN, Chang-Fen HU, Shao-Yu LI
  • Patent number: 12018981
    Abstract: A device includes a scattering structure and a collection structure. The scattering structure is arranged to concurrently scatter incident electromagnetic radiation along a first scattering axis and along a second scattering axis. The first scattering axis and the second scattering axis are non-orthogonal. The collection structure includes a first input port aligned with the first scattering axis and a second input port aligned with the second scattering axis. A method includes scattering electromagnetic radiation along a first scattering axis to create first scattered electromagnetic radiation and along a second scattering axis to create second scattered electromagnetic radiation. The first scattering axis and the second scattering axis are non-orthogonal. The first scattered electromagnetic radiation is detected to yield first detected radiation and the second scattered electromagnetic radiation is detected to yield second detected radiation.
    Type: Grant
    Filed: May 26, 2023
    Date of Patent: June 25, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chewn-Pu Jou, Feng Wei Kuo, Huan-Neng Chen, Lan-Chou Cho
  • Publication number: 20240160080
    Abstract: In an embodiment, a phase shifter includes: a light input end; a light output end; a p-type semiconductor material, and an n-type semiconductor material contacting the p-type semiconductor material along a boundary area, wherein the boundary area is greater than a length from the light input end to the light output end multiplied by a core width of the phase shifter.
    Type: Application
    Filed: January 26, 2024
    Publication date: May 16, 2024
    Inventors: Huan-Neng CHEN, Chewn-Pu JOU, Lan-Chou CHO, Feng-Wei KUO
  • Publication number: 20240151908
    Abstract: Disclosed is a system and method for communication using an efficient fiber-to-chip grating coupler with a high coupling efficiency.
    Type: Application
    Filed: January 19, 2024
    Publication date: May 9, 2024
    Inventors: Feng-Wei KUO, Lan-Chou CHO, Huan-Neng CHEN, Chewn-Pu JOU
  • Patent number: 11967958
    Abstract: In some embodiments, digital logic components, such as those found in standard cells in integrated circuit devices, are used to synthesize signals with controllable waveforms that result in transmitted signals that meet certain requirements, such as above-threshold high openings and below-threshold over/under-shooting. In some embodiments, driving buffers with logic controls and delay chains are used to achieve controllable slew rates at rising and falling edges to minimize over/under shooting behavior in signals. In some embodiments, control logic and delay chains produce controllable rising/falling “stair-type” edges to obtain optimized damping waveform.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huan-Neng Chen, Chang-Fen Hu, Shao-Yu Li
  • Patent number: 11966241
    Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Neng Chen, Yen-Lin Liu, Chia-Wei Hsu, Jo-Yu Wu, Chang-Fen Hu, Shao-Yu Li, Bo-Ting Chen
  • Patent number: 11927806
    Abstract: Disclosed is a system and method for communication using an efficient fiber-to-chip grating coupler with a high coupling efficiency.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng-Wei Kuo, Lan-Chou Cho, Huan-Neng Chen, Chewn-Pu Jou
  • Patent number: 11914265
    Abstract: In an embodiment, a phase shifter includes: a light input end; a light output end; a p-type semiconductor material, and an n-type semiconductor material contacting the p-type semiconductor material along a boundary area, wherein the boundary area is greater than a length from the light input end to the light output end multiplied by a core width of the phase shifter.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huan-Neng Chen, Chewn-Pu Jou, Lan-Chou Cho, Feng-Wei Kuo
  • Publication number: 20230387180
    Abstract: In an embodiment, a circuit includes: a transformer defining an inductive footprint within a first layer; a grounded shield bounded by the inductive footprint within a second layer separate from the first layer; and a circuit component bounded by the inductive footprint within a third layer separate from the second layer, wherein: the circuit component is coupled with the transformer through the second layer, and the third layer is separated from the first layer by the second layer.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Feng Wei KUO, Chewn-Pu Jou, Huan-Neng Chen, Lan-Chou Cho, Robert Bogdan Staszewski