Patents by Inventor Huan-Neng CHEN

Huan-Neng CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11699669
    Abstract: A method includes: forming an interconnect structure over a semiconductor substrate. The interconnect structure includes: a magnetic core and a conductive coil winding around the magnetic core and electrically insulated from the magnetic core, wherein the conductive coil has horizontally-extending conductive lines and vertically-extending conductive vias electrically connecting the horizontally-extending conductive lines, wherein the magnetic core and the conductive coil are arranged in an inductor zone of the interconnect structure. The interconnect structure also includes a dielectric material electrically insulating the magnetic core from the conductive coil, and a connecting metal line adjacent to and on the outside of the inductor zone. The connecting metal line is electrical isolated from the inductor zone. The connecting metal line includes an upper surface lower than an upper surface of the second conductive vias and a bottom surface higher than a bottom surface of the first conductive vias.
    Type: Grant
    Filed: June 26, 2022
    Date of Patent: July 11, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wen-Shiang Liao, Huan-Neng Chen
  • Publication number: 20230194908
    Abstract: An optical modulator includes a carrier and a waveguide disposed on the carrier. The waveguide includes a first optical coupling region, a second optical coupling region, first regions, and second regions. The first optical coupling region is doped with first dopants. The second optical coupling region abuts the first optical coupling region and is doped with second dopants. The first dopants and the second dopants are of different conductivity type. The first regions are doped with the first dopants and are arrange adjacent to the first optical coupling region. The first regions have respective increasing doping concentrations as distances of the first regions increase from the first optical coupling region. The second regions are doped with the second dopants and are arranged adjacent to the second optical coupling region. The second regions have respective increasing doping concentrations as distances of the second regions increase from the second optical coupling region.
    Type: Application
    Filed: February 8, 2023
    Publication date: June 22, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lan-Chou Cho, Chewn-Pu Jou, Feng-Wei KUO, Huan-Neng Chen, Min-Hsiang Hsu
  • Patent number: 11682638
    Abstract: A method of forming a semiconductor structure is provided. A first inter-level dielectric (ILD) layer is formed overlying a molding layer. The first ILD layer is patterned to form a plurality of first openings. A first lower transmitter electrode and a first lower receiver electrode are formed by depositing a first metal material within the plurality of first openings. A first dielectric waveguide is formed overlying the first ILD layer, the first lower transmitter electrode and the first lower receiver electrode. A second ILD layer is formed overlying the first dielectric waveguide and includes a plurality of second openings. A second lower transmitter electrode and a second lower receiver electrode are formed by depositing a second metal material within the plurality of second openings. A second dielectric waveguide is formed overlying the second ILD layer, the second lower transmitter electrode and the second lower receiver electrode.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: June 20, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wen-Shiang Liao, Huan-Neng Chen
  • Patent number: 11652136
    Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a molding layer and a first capacitor. The first capacitor includes a first vertical conductive structure within the molding layer, a second vertical conductive structure within the molding layer, and a first high-k dielectric material between the first vertical conductive structure and the second vertical conductive structure.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: May 16, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Huan-Neng Chen, Wen-Shiang Liao
  • Patent number: 11635643
    Abstract: An optical attenuating structure is provided. The optical attenuating structure includes a substrate, a waveguide, doping regions, an optical attenuating member, and a dielectric layer. The waveguide is extended over the substrate. The doping regions are disposed over the substrate, and include a first doping region, a second doping region opposite to the first doping region and separated from the first doping region by the waveguide, a first electrode extended over the substrate and in the first doping region, and a second electrode extended over the substrate and in the second doping region. The first optical attenuating member is coupled with the waveguide and disposed between the waveguide and the first electrode. The dielectric layer is disposed over the substrate and covers the waveguide, the doping regions and the first optical attenuating member.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: April 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Huan-Neng Chen, Feng-Wei KUo, Min-Hsiang Hsu, Lan-Chou Cho, Chewn-Pu Jou, Wen-Shiang Liao
  • Patent number: 11637078
    Abstract: A semiconductor package includes a first semiconductor device, a second semiconductor device vertically positioned above the first semiconductor device, and a ground shielded transmission path. The ground shielded transmission path couples the first semiconductor device to the second semiconductor device. The ground shielded transmission path includes a first signal path extending longitudinally between a first end and a second end. The first signal path includes a conductive material. A first insulating layer is disposed over the signal path longitudinally between the first end and the second end. The first insulating layer includes an electrically insulating material. A ground shielding layer is disposed over the insulating material longitudinally between the first end and the second end of the signal path. The ground shielding layer includes a conductive material coupled to ground.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: April 25, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng Wei Kuo, Wen-Shiang Liao, Chewn-Pu Jou, Huan-Neng Chen, Lan-Chou Cho, William Wu Shen
  • Publication number: 20230111170
    Abstract: A semiconductor structure according to the present disclosure includes a buried oxide layer, a first dielectric layer disposed over the buried oxide layer, a first waveguide feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first waveguide feature, a third dielectric layer disposed over the second dielectric layer, and a second waveguide feature disposed in the second dielectric layer and the third dielectric layer. The second waveguide feature is disposed over the first waveguide feature and a portion of the second waveguide feature vertically overlaps a portion of the first waveguide feature.
    Type: Application
    Filed: December 9, 2022
    Publication date: April 13, 2023
    Inventors: Chan-Hong Chern, Chih-Chang Lin, Min-Hsiang Hsu, Weiwei Song, Chewn-Pu Jou, Feng-Wei Kuo, Huan-Neng Chen, Lan-Chou Cho
  • Patent number: 11616631
    Abstract: An integrated circuit includes a first through fourth devices positioned over a substrate, the first device including first through third transceivers, the second device including a fourth transceiver, the third device including a fifth transceiver, and the fourth device including a sixth transceiver. A first radio frequency interconnect (RFI) includes the first transceiver coupled to the fourth transceiver through a first guided transmission medium, a second RFI includes the second transceiver coupled to the fifth transceiver through a second guided transmission medium, and a third RFI includes the third transceiver coupled to the sixth transceiver by the second guided transmission medium.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: March 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huan-Neng Chen, William Wu Shen, Chewn-Pu Jou, Feng Wei Kuo, Lan-Chou Cho, Tze-Chiang Huang, Jack Liu, Yun-Han Lee
  • Publication number: 20230084445
    Abstract: A method of manufacturing the semiconductor structure includes: providing a substrate; forming a first conductive via and a second conductive via extending in the substrate; depositing a first dielectric layer over the substrate and the first and second conductive vias; receiving a waveguide; moving the waveguide to a location over the first dielectric layer and aligning the waveguide with a position of the first dielectric layer; attaching the waveguide to the position of the first dielectric layer; forming a first conductive member and a second conductive member over the waveguide, the first conductive member and the second conductive member being in contact with the waveguide; and etching a backside of the substrate to electrically expose the first and second conductive vias. The first conductive member or the second conductive member is electrically connected to the first or second conductive via.
    Type: Application
    Filed: November 17, 2022
    Publication date: March 16, 2023
    Inventors: HUAN-NENG CHEN, WEN-SHIANG LIAO
  • Publication number: 20230009027
    Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.
    Type: Application
    Filed: February 11, 2022
    Publication date: January 12, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Neng Chen, Yen-Lin LIU, Chia-Wei Hsu, Jo-Yu Wu, CHANG-FEN HU, Shao-Yu Li, Bo-Ting Chen
  • Patent number: 11531159
    Abstract: A semiconductor structure according to the present disclosure includes a buried oxide layer, a first dielectric layer disposed over the buried oxide layer, a first waveguide feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first waveguide feature, a third dielectric layer disposed over the second dielectric layer, and a second waveguide feature disposed in the second dielectric layer and the third dielectric layer. The second waveguide feature is disposed over the first waveguide feature and a portion of the second waveguide feature vertically overlaps a portion of the first waveguide feature.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chan-Hong Chern, Lan-Chou Cho, Huan-Neng Chen, Min-Hsiang Hsu, Feng-Wei Kuo, Chih-Chang Lin, Weiwei Song, Chewn-Pu Jou
  • Patent number: 11532573
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a first die on a first substrate, a second die on a second substrate separate from the first substrate, a transmission line in a redistribution layer on a wafer, and a magnetic structure surrounds the transmission line. The first transmission line electrically connects the first die and the second die. The magnetic structure is configured to increase the characteristic impedance of the transmission line, which can save the current and power consumption of a current mirror and amplifier in a 3D IC chip-on-wafer-on-substrate (CoWoS) semiconductor package.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wen-Shiang Liao, Huan-Neng Chen
  • Patent number: 11528053
    Abstract: A communication system includes a transmitter configured to transmit a modulated signal, a transmission line configured to carry the modulated signal, and a receiver coupled to the transmitter by the transmission line, and configured to receive the modulated signal. The transmitter includes a modulator configured to generate the modulated signal responsive to a data signal and a carrier signal. The receiver includes a demodulator configured to demodulate the modulated signal responsive to a first carrier signal. The demodulator includes a filter and a gain adjusting circuit configured to adjust a gain of the filter, and to generate the set of control signals based on a voltage of the filtered first signal and a voltage of the first signal. The gain adjusting circuit includes a first peak detector coupled to the filter, and configured to detect a peak value of the voltage of the filtered first signal.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Feng Wei Kuo, Huan-Neng Chen, Lan-Chou Cho, Chewn-Pu Jou, William Wu Shen
  • Publication number: 20220373748
    Abstract: An optical attenuating structure is provided. The optical attenuating structure includes a substrate, a waveguide, doping regions, an optical attenuating member, and a dielectric layer. The waveguide is extended over the substrate. The doping regions are disposed over the substrate, and include a first doping region, a second doping region opposite to the first doping region and separated from the first doping region by the waveguide, a first electrode extended over the substrate and in the first doping region, and a second electrode extended over the substrate and in the second doping region. The first optical attenuating member is coupled with the waveguide and disposed between the waveguide and the first electrode. The dielectric layer is disposed over the substrate and covers the waveguide, the doping regions and the first optical attenuating member.
    Type: Application
    Filed: August 8, 2022
    Publication date: November 24, 2022
    Inventors: HUAN-NENG CHEN, FENG-WEI KUO, MIN-HSIANG HSU, LAN-CHOU CHO, CHEWN-PU JOU, WEN-SHIANG LIAO
  • Publication number: 20220373854
    Abstract: In an embodiment, a phase shifter includes: a light input end; a light output end; a p-type semiconductor material, and an n-type semiconductor material contacting the p-type semiconductor material along a boundary area, wherein the boundary area is greater than a length from the light input end to the light output end multiplied by a core width of the phase shifter.
    Type: Application
    Filed: August 4, 2022
    Publication date: November 24, 2022
    Inventors: Huan-Neng CHEN, Chewn-Pu JOU, Lan-Chou CHO, Feng-Wei KUO
  • Patent number: 11509346
    Abstract: A transceiver disposed on a first die in a bidirectional differential die-to-die communication system is disclosed. The transceiver includes a transmission section configured to modulate a first data onto a carrier signal having a first frequency for transmission via a bidirectional differential transmission line; and a reception section configured to receive signals from the bidirectional differential transmission line, the reception section including a filter configured to pass frequencies within a first passband that includes a second frequency, the first frequency being outside of the first passband. According to some embodiments, the reception section is configured to receive, via the bidirectional differential transmission line, modulated data at the second frequency at a same time that the transmission section transmits the modulated data at the first frequency.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: November 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Huan-Neng Chen, Chewn-Pu Jou, Feng-Wei Kuo, Lan-Chou Cho, William Wu Shen
  • Patent number: 11508677
    Abstract: A semiconductor structure and a method of forming the same are provided. A method of manufacturing the semiconductor structure includes: providing a substrate; depositing a first dielectric layer over the substrate; attaching a waveguide to the first dielectric layer; depositing a second dielectric layer to laterally surround the waveguide; and forming a first conductive member and a second conductive member over the second dielectric layer and the waveguide, wherein the first conductive member and the second conductive member are in contact with the waveguide. The waveguide is configured to transmit an electromagnetic signal between the first conductive member and the second conductive member.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Huan-Neng Chen, Wen-Shiang Liao
  • Publication number: 20220352880
    Abstract: In some embodiments, digital logic components, such as those found in standard cells in integrated circuit devices, are used to synthesize signals with controllable waveforms that result in transmitted signals that meet certain requirements, such as above-threshold high openings and below-threshold over/under-shooting. In some embodiments, driving buffers with logic controls and delay chains are used to achieve controllable slew rates at rising and falling edges to minimize over/under shooting behavior in signals. In some embodiments, control logic and delay chains produce controllable rising/falling “stair-type” edges to obtain optimized damping waveform.
    Type: Application
    Filed: November 30, 2021
    Publication date: November 3, 2022
    Inventors: Huan-Neng Chen, Chang-Fen Hu, Shao-Yu Li
  • Publication number: 20220350177
    Abstract: A method of forming semiconductor device includes forming an active layer in a substrate including forming components of one or more transistors; forming an MD and gate (MDG) layer over the active layer including forming a gate line; forming a metal-to-S/D (MD) contact structure; and forming a waveguide between the gate line and the MD contact structure; forming a first interconnection layer over the MDG layer including forming a first via contact structure over the gate line; forming a second via contact structure over the MD contact structure; and forming a heater between the first and second via contact structures and over the waveguide.
    Type: Application
    Filed: July 14, 2022
    Publication date: November 3, 2022
    Inventors: Feng-Wei KUO, Chewn-Pu JOU, Huan-Neng CHEN, Lan-Chou CHO
  • Publication number: 20220336384
    Abstract: A semiconductor structure includes: a substrate; a first dielectric layer over the substrate; a waveguide over the first dielectric layer; a second dielectric layer over the first dielectric layer and laterally surrounding the waveguide; a first conductive member and a second conductive member over the second dielectric layer and the waveguide, the first conductive member and the second conductive member being in contact with the waveguide; a conductive bump on one side of the substrate and electrically connected to the first conductive member or the second conductive member; and a conductive via extending through the substrate and electrically connecting the conductive bump to the first conductive member or the second conductive member. The waveguide is configured to transmit an electromagnetic signal between the first conductive member and the second conductive member.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: HUAN-NENG CHEN, WEN-SHIANG LIAO