Patents by Inventor Huan-Tsung Huang
Huan-Tsung Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11621351Abstract: The present disclosure is generally directed to semiconductor structures and methods that improve breakdown characteristics in finFET device designs, while retaining cost effectiveness for integration into the process flow. The semiconductor structure includes an extended lightly-doped-drain (LDD) region formed on a source/drain structure. The extended LDD regions provide extra separation between source and drain regions, which in turn provides for an increased source to drain resistance. The increased source to drain resistance improves the breakdown voltage of the semiconductor device, and significantly reduces its susceptibility to latch-up. The source to drain resistance may be tuned by adjusting the length of epi block regions, and may also be tuned by selecting desired doping profiles for the LDD and source/drain regions. The length of epi block regions may also be adjusted to maintain high uniformity of epitaxial growth in the S/D regions.Type: GrantFiled: May 3, 2021Date of Patent: April 4, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Hsin Hu, Huan-Tsung Huang
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Publication number: 20210257487Abstract: The present disclosure is generally directed to semiconductor structures and methods that improve breakdown characteristics in finFET device designs, while retaining cost effectiveness for integration into the process flow. The semiconductor structure includes an extended lightly-doped-drain (LDD) region formed on a source/drain structure. The extended LDD regions provide extra separation between source and drain regions, which in turn provides for an increased source to drain resistance. The increased source to drain resistance improves the breakdown voltage of the semiconductor device, and significantly reduces its susceptibility to latch-up. The source to drain resistance may be tuned by adjusting the length of epi block regions, and may also be tuned by selecting desired doping profiles for the LDD and source/drain regions. The length of epi block regions may also be adjusted to maintain high uniformity of epitaxial growth in the S/D regions.Type: ApplicationFiled: May 3, 2021Publication date: August 19, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Hsin HU, Huan-Tsung HUANG
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Patent number: 10998443Abstract: The present disclosure is generally directed to semiconductor structures and methods that improve breakdown characteristics in finFET device designs, while retaining cost effectiveness for integration into the process flow. The semiconductor structure includes an extended lightly-doped-drain (LDD) region formed on a source/drain structure. The extended LDD regions provide extra separation between source and drain regions, which in turn provides for an increased source to drain resistance. The increased source to drain resistance improves the breakdown voltage of the semiconductor device, and significantly reduces its susceptibility to latch-up. The source to drain resistance may be tuned by adjusting the length of epi block regions, and may also be tuned by selecting desired doping profiles for the LDD and source/drain regions. The length of epi block regions may also be adjusted to maintain high uniformity of epitaxial growth in the S/D regions.Type: GrantFiled: April 15, 2016Date of Patent: May 4, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Hsin Hu, Huan-Tsung Huang
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Patent number: 10679723Abstract: Disclosed is a system and method for performing direct memory characterization of memory cells in a memory array using peripheral transistors. A memory array is fabricated using a mask layer defining routing for a set of first stage periphery transistors electrically connected to the word lines of the memory array. A revised mask is used for defining a different routing for a set of second stage periphery transistors including different characteristics than the first stage periphery transistors. Testing is conducted by applying a simulated Erase signal to the nonvolatile memory cells and determining which cells are erased. Based on this test, certain characteristics of the first and/or second stage periphery transistors can be identified that provide improved conditions for the nonvolatile memory cells. A product chip can be manufactured using modified versions of the first stage periphery transistors that incorporate the characteristics that provide the improved condition(s).Type: GrantFiled: December 6, 2018Date of Patent: June 9, 2020Assignee: PDF SOLUTIONS, INC.Inventors: Dong Kyu Lee, Kelvin Yih-Yuh Doong, Tuan Pham, Klaus Schuegraf, Christoph Dolainsky, Huan Tsung Huang, Hendrik Schneider
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Patent number: 9812444Abstract: A semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a fin extending away from a substrate, a plurality of epitaxially grown regions disposed along a top surface of the fin, and at least two contacts that provide electrical contact to the fin. The plurality of epitaxially grown regions are arranged to alternate with regions having no epitaxial material grown on the top surface of the fin. A resistance exists between the two contacts that is at least partially based on the arrangement of the plurality of epitaxially grown regions.Type: GrantFiled: May 11, 2017Date of Patent: November 7, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Hsin Hu, Hsueh-Shih Fan, Huan-Tsung Huang
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Publication number: 20170301785Abstract: The present disclosure is generally directed to semiconductor structures and methods that improve breakdown characteristics in finFET device designs, while retaining cost effectiveness for integration into the process flow. The semiconductor structure includes an extended lightly-doped-drain (LDD) region formed on a source/drain structure. The extended LDD regions provide extra separation between source and drain regions, which in turn provides for an increased source to drain resistance. The increased source to drain resistance improves the breakdown voltage of the semiconductor device, and significantly reduces its susceptibility to latch-up. The source to drain resistance may be tuned by adjusting the length of epi block regions, and may also be tuned by selecting desired doping profiles for the LDD and source/drain regions. The length of epi block regions may also be adjusted to maintain high uniformity of epitaxial growth in the S/D regions.Type: ApplicationFiled: April 15, 2016Publication date: October 19, 2017Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Hsin HU, Huan-Tsung Huang
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Publication number: 20170263602Abstract: A semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a fin extending away from a substrate, a plurality of epitaxially grown regions disposed along a top surface of the fin, and at least two contacts that provide electrical contact to the fin. The plurality of epitaxially grown regions are arranged to alternate with regions having no epitaxial material grown on the top surface of the fin. A resistance exists between the two contacts that is at least partially based on the arrangement of the plurality of epitaxially grown regions.Type: ApplicationFiled: May 11, 2017Publication date: September 14, 2017Inventors: Chia-Hsin HU, Hsueh-Shih Fan, Huan-Tsung Huang
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Patent number: 9691758Abstract: A semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a fin extending away from a substrate, a plurality of epitaxially grown regions disposed along a top surface of the fin, and at least two contacts that provide electrical contact to the fin. The plurality of epitaxially grown regions are arranged to alternate with regions having no epitaxial material grown on the top surface of the fin. A resistance exists between the two contacts that is at least partially based on the arrangement of the plurality of epitaxially grown regions.Type: GrantFiled: March 11, 2016Date of Patent: June 27, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Hsin Hu, Hsueh-Shih Fan, Huan-Tsung Huang
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Patent number: 9443925Abstract: Leakage current can be substantially reduced by the formation of a seal dielectric in place of the conventional junction between source/drain region(s) and the substrate material. Trenches are formed in the substrate and lined with a seal dielectric prior to filling the trenches with semiconductor material. Preferably, the trenches are overfilled and a CMP process planarizes the overfill material. An epitaxial layer can be grown atop the trenches after planarization, if desired.Type: GrantFiled: September 11, 2015Date of Patent: September 13, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huan-Tsung Huang, Kuo-Cheng Wu, Carlos H. Diaz
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Publication number: 20160005807Abstract: Leakage current can be substantially reduced by the formation of a seal dielectric in place of the conventional junction between source/drain region(s) and the substrate material. Trenches are formed in the substrate and lined with a seal dielectric prior to filling the trenches with semiconductor material. Preferably, the trenches are overfilled and a CMP process planarizes the overfill material. An epitaxial layer can be grown atop the trenches after planarization, if desired.Type: ApplicationFiled: September 11, 2015Publication date: January 7, 2016Inventors: Huan-Tsung Huang, Kuo-Cheng Wu, Carlos H. Diaz
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Patent number: 9136329Abstract: Leakage current can be substantially reduced by the formation of a seal dielectric in place of the conventional junction between source/drain region(s) and the substrate material. Trenches are formed in the substrate and lined with a seal dielectric prior to filling the trenches with semiconductor material. Preferably, the trenches are overfilled and a CMP process planarizes the overfill material. An epitaxial layer can be grown atop the trenches after planarization, if desired.Type: GrantFiled: March 5, 2013Date of Patent: September 15, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huan-Tsung Huang, Kuo-Cheng Wu, Carlos H. Diaz
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Patent number: 8754487Abstract: The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a first metal layer on the high k dielectric material layer; forming a silicon layer on the first metal layer; patterning the silicon layer, the first metal layer and the high k dielectric material layer to form a gate stack; and performing a silicidation process to fully change the silicon layer into a silicide electrode.Type: GrantFiled: December 14, 2012Date of Patent: June 17, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yuri Masuoka, Huan-Tsung Huang
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Patent number: 8679926Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension.Type: GrantFiled: September 14, 2011Date of Patent: March 25, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huan-Tsung Huang, Shyh-Horng Yang, Yuri Masuoka, Ken-Ichi Goto
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Patent number: 8415749Abstract: Leakage current can be substantially reduced by the formation of a seal dielectric in place of the conventional junction between source/drain region(s) and the substrate material. Trenches are formed in the substrate and lined with a seal dielectric prior to filling the trenches with semiconductor material. Preferably, the trenches are overfilled and a CMP process planarizes the overfill material. An epitaxial layer can be grown atop the trenches after planarization, if desired.Type: GrantFiled: April 19, 2007Date of Patent: April 9, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huan-Tsung Huang, Kou-Cheng Wu, Carlos H. Diaz
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Patent number: 8357581Abstract: The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a first metal layer on the high k dielectric material layer; forming a silicon layer on the first metal layer; patterning the silicon layer, the first metal layer and the high k dielectric material layer to form a gate stack; and performing a silicidation process to fully change the silicon layer into a silicide electrode.Type: GrantFiled: August 25, 2011Date of Patent: January 22, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yuri Masuoka, Huan-Tsung Huang
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Patent number: 8324090Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first capping layer and a second capping layer over the high-k dielectric layer, the first capping layer overlying the first region and the second capping layer overlying the second region, forming a layer containing silicon (Si) over the first and second capping layers, forming a metal layer over the layer containing Si, and forming a first gate stack over the first region and a second gate stack over the second active region.Type: GrantFiled: December 18, 2008Date of Patent: December 4, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yuri Masuoka, Peng-Fu Hsu, Huan-Tsung Huang, Kuo-Tai Huang, Yong-Tian Hou, Carlos H. Diaz
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Publication number: 20120003804Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension.Type: ApplicationFiled: September 14, 2011Publication date: January 5, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Huan-Tsung Huang, Shyh-Horng Yang, Yuri Masuoka, Ken-Ichi Goto
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Publication number: 20110303991Abstract: The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a first metal layer on the high k dielectric material layer; forming a silicon layer on the first metal layer; patterning the silicon layer, the first metal layer and the high k dielectric material layer to form a gate stack; and performing a silicidation process to fully change the silicon layer into a silicide electrode.Type: ApplicationFiled: August 25, 2011Publication date: December 15, 2011Inventors: Yuri Masuoka, Huan-Tsung Huang
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Patent number: 8030718Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension.Type: GrantFiled: April 15, 2009Date of Patent: October 4, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huan-Tsung Huang, Shyh-Horng Yang, Yuri Masuoka, Ken-Ichi Goto
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Patent number: 8012817Abstract: The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a first metal layer on the high k dielectric material layer; forming a silicon layer on the first metal layer; patterning the silicon layer, the first metal layer and the high k dielectric material layer to form a gate stack; and performing a silicidation process to fully change the silicon layer into a silicide electrode.Type: GrantFiled: May 8, 2009Date of Patent: September 6, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yuri Masuoka, Huan-Tsung Huang