Abstract: A PMOS (p-channel metal oxide semiconductor) device having at low voltage threshold MOSFET (MOS field effect transistor) with an improved work function and favorable DIBL (drain-induced barrier lowering) and SCE (short channel effect) characteristics, and a method for making such a device. The PMOS device includes a gate structure that is disposed on a substrate and includes a silicided gate electrode. The silicide is preferably nickel-rich and includes a peak platinum concentration at or near the interface between the gate electrode and a dielectric layer that separates the gate electrode from the substrate. The platinum peak region is produced by a multi-step rapid thermal annealing or similar process. The PMOS device may also include two such MOSFETs, one of which is boron-doped and one of which is not.

Abstract: A method for forming a MOS device on a semiconductor substrate includes steps of: forming a gate structure on the semiconductor substrate; implanting ions into the semiconductor substrate for forming one or more lightly doped drain structures adjacent to the gate structure; thermally treating the semiconductor substrate at a first temperature lower than a threshold temperature, below which no substantial transient enhanced diffusion of the lightly doped drain structures occurs, for repairing damage to the semiconductor substrate caused by the ion implantation; forming sidewall spacers to sidewalls of the gate structure on the semiconductor substrate; and forming source and drain regions adjacent to the gate structure in the semiconductor substrate.

Abstract: The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a first metal layer on the high k dielectric material layer; forming a silicon layer on the first metal layer; patterning the silicon layer, the first metal layer and the high k dielectric material layer to form a gate stack; and performing a silicidation process to fully change the silicon layer into a silicide electrode.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first capping layer and a second capping layer over the high-k dielectric layer, the first capping layer overlying the first region and the second capping layer overlying the second region, forming a layer containing silicon (Si) over the first and second capping layers, forming a metal layer over the layer containing Si, and forming a first gate stack over the first region and a second gate stack over the second active region.

Abstract: Leakage current can be substantially reduced by the formation of a seal dielectric in place of the conventional junction between source/drain region(s) and the substrate material. Trenches are formed in the substrate and lined with a seal dielectric prior to filling the trenches with semiconductor material. Preferably, the trenches are overfilled and a CMP process planarizes the overfill material. An epitaxial layer can be grown atop the trenches after planarization, if desired.

Abstract: A PMOS (p-channel metal oxide semiconductor) device having at low voltage threshold MOSFET (MOS field effect transistor) with an improved work function and favorable DIBL (drain-induced barrier lowering) and SCE (short channel effect) characteristics, and a method for making such a device. The PMOS device includes a gate structure that is disposed on a substrate and includes a silicided gate electrode. The silicide is preferably nickel-rich and includes a peak platinum concentration at or near the interface between the gate electrode and a dielectric layer that separates the gate electrode from the substrate. The platinum peak region is produced by a multi-step rapid thermal annealing or similar process. The PMOS device may also include two such MOSFETs, one of which is boron-doped and one of which is not.

Abstract: A method for forming a MOS device on a semiconductor substrate includes steps of: forming a gate structure on the semiconductor substrate; implanting ions into the semiconductor substrate for forming one or more lightly doped drain structures adjacent to the gate structure; thermally treating the semiconductor substrate at a first temperature lower than a threshold temperature, below which no substantial transient enhanced diffusion of the lightly doped drain structures occurs, for repairing damage to the semiconductor substrate caused by the ion implantation; forming sidewall spacers to sidewalls of the gate structure on the semiconductor substrate; and forming source and drain regions adjacent to the gate structure in the semiconductor substrate.

Abstract: A layout for a transistor in a standard cell is disclosed. The layout for a transistor includes an active region with at least one portion having a first edge and at least one portion having a second edge all perpendicular to a channel of the transistor; and a gate placed on top of the active region with a distance from an edge of the gate to the first edge being shorter than a distance from the edge of the gate to the second edge of the active region, wherein the active region is of a non-rectangular shape.

Abstract: A layout for a transistor in a standard cell is disclosed. The layout for a transistor comprises an active region with at least one portion having a first edge and at least one portion having a second edge all perpendicular to a channel of the transistor; and a gate placed on top of the active region with a distance from an edge of the gate to the first edge being shorter than a distance from the edge of the gate to the second edge of the active region, wherein the active region is of a non-rectangular shape.

Abstract: A MOS transistor structure is disclosed. A gate electrode is disposed on a semiconductor substrate. A first extension of a predetermined impurity type is substantially aligned with the gate electrode in the substrate. A second extension of the predetermined impurity type overlaps with the first extension in the substrate. The first extension has at least one lateral boundary line closer to the gate electrode than that of the second extension. Source and drain regions of the predetermined polarity type overlaps with the first and second extensions in the substrate. The second extension has at least one lateral boundary line closer to the gate electrode than that of the source and drain regions. The source and drain regions are deeper than the second extension, which is deeper than the first extension, so that they collectively reduce lateral abruptness of the source and drain, while maintaining a reduced extension resistance.

Abstract: The present disclosure provides a structure and method for determining a parasitic junction voltage that cannot be directly measured because of lack of space for a probe. For example, the method may be used with a test structure having at least two transistors pairs. The first transistor pair may include a shared source or drain associated with a parasitic junction capacitance (Csb1), and two gates spaced to enable direct measurement of Csb1. The second transistor pair may include a shared source or drain associated with a parasitic junction capacitance (Csb2), and two gates spaced to prevent direct measurement of Csb2. The method may involve measuring a first total junction capacitance (C1) of the first transistor pair, measuring Csb1, measuring a second total junction capacitance (C2) of the second transistor pair, and determining Csb2 using C1, C2, and Csb1.

Abstract: The present invention provides methods for manufacturing semiconductor devices. In one embodiment, the method includes forming a gate oxide over a substrate and a gate electrode over the gate oxide. The method also includes implanting impurities into the substrate using the gate electrode as an implant mask to form lightly-doped regions in the substrate. The method further includes forming a first spacer adjacent the gate electrode, and implanting impurities into the substrate and through a portion of the lightly-doped regions using the first spacer as an implant mask to form deep source/drain regions in the substrate. The method still further includes forming a second spacer adjacent the first spacer, implanting impurities into the substrate using the second spacer as an implant mask to form a graded source/drain region in the substrate, and removing the second spacer. Also disclosed is a semiconductor device constructed using the techniques disclosed herein.

Abstract: Stress in a silicon nitride contact etch stop layer on a CMOS structure having NMOS and PMOS devices is selectively relieved by selective implantation of oxygen-containing or carbon-containing ions resulting in there being no tensile stress in areas of the layer above the PMOS devices and no compressive stress in areas of the layer above the NMOS devices.

Abstract: Semiconductor device having improved short channel effects and method of forming thereof. One method includes forming a gate oxide over a substrate and a gate electrode over the gate oxide, and implanting impurities into the substrate using the gate electrode as an implant mask to form a lightly-doped region in the substrate. The method includes depositing second spacer material adjacent to the gate electrode, forming a first spacer on the second spacer material, and implanting impurities into the substrate and through a portion of the lightly-doped region using the first spacer as an implant mask to form a first junction region in the substrate. The method includes removing the first spacer, etching the second spacer material to form a second spacer adjacent the gate electrode, and implanting impurities into the substrate using the second spacer as an implant mask to form a second junction region in the substrate.

Abstract: The present invention provides methods for manufacturing semiconductor devices. In one embodiment, the method includes forming a gate oxide over a substrate and a gate electrode over the gate oxide. The method also includes implanting impurities into the substrate using the gate electrode as an implant mask to form lightly-doped regions in the substrate. The method further includes forming a first spacer adjacent the gate electrode, and implanting impurities into the substrate and through a portion of the lightly-doped regions using the first spacer as an implant mask to form deep source/drain regions in the substrate. The method still further includes forming a second spacer adjacent the first spacer, implanting impurities into the substrate using the second spacer as an implant mask to form a graded source/drain region in the substrate, and removing the second spacer. Also disclosed is a semiconductor device constructed using the techniques disclosed herein.