Abstract: A semiconductor device structure and method that utilizes anti-reflection components. The structure includes at least one ramp VIA formed in a VIA isolator layer, at least one anti-reflection component formed on the at least one ramp VIA. A trench isolator layer is formed on the at least one anti-reflection component, and a photoresist is selectively patterned on the trench isolator layer. The trench isolator layer and a portion of the at least one anti-reflection component is etched based upon the selectively patterned photoresist to form a trench metal component hole above the at least one ramp VIA. Thereafter, a trench metal component is formed in the trench metal component hole.

Abstract: An integrated circuit device and a method of manufacturing the same are provided. The method includes steps of: forming a semiconductor device on a substrate; forming a first interconnect structure and a dielectric layer over the semiconductor device; and forming a second interconnect structure over the first interconnect structure, wherein the formation of the second interconnect structure includes: forming an insulating film over the first interconnect structure; depositing an etch stop layer over the insulating film, wherein the etch stop layer and the insulating film include different materials; depositing an isolation layer over the etch stop layer; performing a first etching operation to form a via penetrating the isolation layer and exposing the etch stop layer; and performing a second etching operation to extend the via downward to penetrate the etch stop layer and the insulating film and expose a portion of the first interconnect structure.

Abstract: A damping device is provided. The damping device includes a damper including a mechanical deflector. The damping device includes a post coupled to the mechanical deflector. The damping device includes a case in which the damper is disposed.

Abstract: A memory device includes a bottom electrode, a resistance switching element over the bottom electrode, a top electrode over the resistance switching element, and a dielectric layer. The dielectric layer surrounds the bottom electrode, the resistance switching element, and the top electrode. The resistance switching element has a first portion between the top electrode and the dielectric layer.

Abstract: The present disclosure provides for an automated spray system (100) to produce an elastomeric pad on a railroad tie. The automated spray system (100) includes a two-component spray system (102) for spraying a two-component reaction mixture to produce the elastomeric pad on the railroad tie. The automated spray system further includes a gantry system (140) having girder (146) that supports the spray applicator.

Abstract: A semiconductor substrate processing method includes: providing a substrate to be processed, where the substrate to be processed has a side to be processed and a bonding side which are opposite to each other; providing a hole supply substrate; and bonding the hole supply substrate to the bonding side of the substrate to be processed by a wafer bonding process so as to obtain a substrate pair, and performing a material process. By the semiconductor substrate processing method, the purpose of rapid electrochemical etching can be achieved.

Abstract: A device structure may include an interconnect-level dielectric material layer located over a substrate, a first metal interconnect structure embedded in the interconnect-level dielectric material layer and including a first metallic barrier liner and a first metallic fill material portion, and an overlying dielectric material layer. An opening in the overlying dielectric material layer may be formed entirely within an area of the first metallic barrier layer and outside the area of the first metallic fill material portion to reduce plasma damage. A second metal interconnect structure contacting a top surface of the first metallic barrier liner may be formed in the opening. An entirety of a top surface the first metallic fill material portion contacts a bottom surface of the overlying dielectric material layer.

Abstract: The present invention provides a spine stabilization system comprising: a wire; a first fixation member connected to the wire; and an auxiliary fixation device. The auxiliary fixation device comprises: a main body portion; a needle portion connected to the main body portion, wherein a portion of the wire is disposed within the needle portion, and the wire and the first fixation member are able to move relative to the needle portion; a push rod portion partially arranged in the needle portion and is able to move relative to the needle portion; and a control portion connected to the push rod portion. The control portion causes the push rod portion to move relative to the needle portion, so that the wire and the first fixation member move relative to the needle portion by means of the push rod portion.

Abstract: A damping device is provided. The damping device includes a damper including a mechanical deflector. The damping device includes a post coupled to the mechanical deflector. The damping device includes a case in which the damper is disposed.

Abstract: Devices and methods of manufacture for a graduated, “step-like,” semiconductor structure having two or more resonator trenches. A semiconductor structure may comprise a first resonator and a second resonator. The first resonator comprising a first metallic resonance layer and a capping plate having a bottom surface that is a first distance from a distal end of the first metallic resonance layer 128. The second resonator comprising a second metallic resonance layer and the capping plate, in which the bottom surface is a second distance from a from a distal end of the second metallic resonance layer 128b, and in which first distance is different from the second distance.

Abstract: A RRAM device is provided. The RRAM device includes: a bottom electrode in a first dielectric layer; a switching layer in a second dielectric layer over the first dielectric layer, wherein a conductive path is formed in the switching layer when a forming voltage is applied; and a needle-like-shaped top electrode region in a third dielectric layer over the second dielectric layer. The needle-like-shaped top electrode region includes: an oxygen-rich dielectric layer, wherein a lower end of the oxygen-rich dielectric layer is a tip; and a top electrode over the oxygen-rich dielectric layer.

Abstract: Systems and methods are provided for testing sockets, such as but not limited to CPU and GPU sockets. Systems and methods disclosed herein utilize a test card that has a test component and an adaptor Printed Circuit Board. The adaptor Printed Circuit Board (PCB) is configured to connect with a corresponding socket type on a motherboard and serves as an interface between the test component and a socket of the corresponding socket type. The test component includes logic that simulates a test function to test the socket. By connecting the test card to a socket using the adaptor PCB, the socket can be tested by simulating the test function on the test card.

Abstract: Pyrimidine compounds of formula (I) shown herein. Also disclosed are pharmaceutical compositions containing one of the pyrimidine compounds and methods of using the pyrimidine compounds to treat or prevent chemotherapy-induced peripheral neuropathy.

Abstract: A device structure may include an interconnect-level dielectric material layer located over a substrate, a first metal interconnect structure embedded in the interconnect-level dielectric material layer and including a first metallic barrier liner and a first metallic fill material portion, and an overlying dielectric material layer. An opening in the overlying dielectric material layer may be formed entirely within an area of the first metallic barrier layer and outside the area of the first metallic fill material portion to reduce plasma damage. A second metal interconnect structure contacting a top surface of the first metallic barrier liner may be formed in the opening. An entirety of a top surface the first metallic fill material portion contacts a bottom surface of the overlying dielectric material layer.

Abstract: Devices and methods of manufacture for a graduated, “step-like,” capacitance structure having two or more capacitors. A semiconductor structure comprising a capacitor structure, the capacitor structure comprising a first capacitor and a second capacitor. The first capacitor comprising a first bottom electrode and a top electrode having a bottom surface that is a first distance from a top surface of the first bottom electrode. The second capacitor comprising a second bottom electrode and the top electrode, in which the bottom surface is a second distance from a top surface of the second bottom electrode, and in which the first distance is different from the second distance.

Abstract: Devices and methods of manufacture for a graduated, “step-like,” semiconductor structure having two or more resonator trenches. A semiconductor structure may comprise a first resonator and a second resonator. The first resonator comprises a first metallic resonance layer and a capping plate having a bottom surface that is a first distance from a distal end of the first metallic resonance layer. The second resonator comprises a second metallic resonance layer and the capping plate, in which the bottom surface is a second distance from a from a distal end of the second metallic resonance layer, and in which first distance is different from the second distance.

Abstract: Interconnect structures and methods of forming interconnect structures are disclosed that provide decreased risk of unwanted via formation through interconnect-level dielectric layers. A method of forming an interconnect structure includes forming first and second dielectric layers over a first metal interconnect feature, where the dielectric layers include localized elevated regions caused by a hillock in the first metal interconnect feature. A planarization process removes the localized elevated region of the second dielectric layer, and third and fourth dielectric layers are formed over the planar upper surface of the second dielectric layer. An etching process through the third and fourth dielectric layers, and into the second dielectric layer, provides a trench having a planar bottom surface.

Abstract: A cavity may be formed in a dielectric material layer overlying a substrate. A layer stack including a metallic barrier liner, a metallic fill material layer, and a metallic capping material may be deposited in the cavity and over the dielectric material layer. Portions of the layer stack located above a horizontal plane including a top surface of the dielectric material layer may be removed. A contiguous set of remaining material portions of the layer stack includes a metal interconnect structure that is free of a pitted surface.

Abstract: A cavity may be formed in a dielectric material layer overlying a substrate. A layer stack including a metallic barrier liner, a metallic fill material layer, and a metallic capping material may be deposited in the cavity and over the dielectric material layer. Portions of the layer stack located above a horizontal plane including a top surface of the dielectric material layer may be removed. A contiguous set of remaining material portions of the layer stack includes a metal interconnect structure that is free of a pitted surface.

Abstract: A polyurethane adhesive composition, more specifically a two-component polyurethane adhesive, including (a) at least one isocyanate component, wherein the isocyanate component comprises (ai) at least one first polyisocyanate compound, and (aii) at least one second polyisocyanate compound having a functionality of greater than, or equal to, about 2.3; and (b) at least one polyol component; and a process for making the above adhesive composition.