Abstract: A method of controlling a battery-powered remote controller to decrease a duty cycle to allow continued operations despite the quantity of the battery is bad. The method determines a drop in voltage of the battery in standby mode as voltage of the battery is being read. When receiving a command to activate a voice function, determining whether the drop in voltage in the standby mode is greater than or equal to a preset value. If the drop is greater than or equal to the preset value, the method then determines whether the drop in voltage falls in a preset range. If the drop falls in the preset range, the method regulates a duty cycle of the pulse signal activating the voice function, and activates the voice function as required. A remote controller and a non-transitory storage medium are also provided.

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

Abstract: An aircraft passenger suite is provided. The suite comprises an aircraft seat for use by a passenger. The suite also comprises a controller for controlling a number of output states of the suite, the controller comprising a logic condition receiver operable to receive a logic condition input. The suite also comprises sensor equipment operable to provide a sensor input to the controller, the sensor input providing an indication of at least one attribute of a passenger of the suite. The sensor equipment comprises one or more of: an image sensor a pressure sensor and a physiological sensor. The controller is configured to control at least one of the output states of the suite based on both the logic condition input and the sensor input.

Abstract: An integrated circuit design implementation system includes a die-to-die (D2D) complier configured to receive a configuration of a semiconductor package. The semiconductor package includes a first semiconductor die and a second semiconductor die bonded to each other. The D2D compiler is configured to generate, based on the configuration of the semiconductor package, a first bump map and a second bump map for the first semiconductor die and the second semiconductor die, respectively. The first bump map indicates respective locations of a plurality of first bump structures of the first semiconductor die, and the second bump map indicates respective locations of a plurality of second bump structures of the second semiconductor die.

Abstract: The present application discloses a semiconductor device with an interface structure. The interface structure includes an interface board configured to be fixed onto and electrically coupled to a chuck of a testing equipment, and a first object positioned on a first surface of the interface board and electrically coupled to the interface board. The first object is configured to be analyzed by the testing equipment.

Abstract: An optical transceiver system includes a laser diode device. The laser diode device includes a first submount, a second submount, a laser diode, and a bump. The first submount includes a first electrode. The second submount corresponds to the first submount and includes a second electrode. The laser diode is between the first submount and the second submount, and a side of the laser diode adjacent to the first submount is electrically connected to the first electrode. The laser diode has a waveguide and the waveguide is on a side of the laser diode away from the first submount. The bump corresponds to the waveguide, one of two ends of the bump is electrically connected to the second electrode, and a height of the bump is substantially higher than a height of the waveguide.

Abstract: A high voltage device includes: a semiconductor layer, a well, a body region, a body contact, a gate, a source, and a drain. The body contact is configured as an electrical contact of the body region. The body contact and the source overlap with each other to define an overlap region. The body contact has a depth from an upper surface of the semiconductor layer, wherein the depth is deeper than a depth of the source, whereby a part of the body contact is located vertically below the overlap region. A length of the overlap region in a channel direction is not shorter than a predetermined length, so as to suppress a parasitic bipolar junction transistor from being turning on when the high voltage device operates, wherein the parasitic bipolar junction transistor is formed by a part of the well, a part of the body region and a part of the source.

Abstract: A method in certain embodiments includes using a computer system that includes an EDA tool to generate a layout of an IC device; searching, using a statistical method such as Bayesian optimization process, for one or more input variable parameters, such as the dimensions of the IC device and the dimensions of the voltage areas in the IC device, that results in an optimal characteristic, such as power, performance or area (PPA) of the IC device, subject to a limiting condition, such as one determined using a cost function. A computer system including one or more EDAs configured to perform the method is also disclosed.

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

Abstract: Embodiments of this specification provide a table data query method, a table data query apparatus, and a system that are of a distributed database. In response to that a table data processing node executes a first execution subplan to read row data of a driving table, the table data query apparatus generates a data rescanning instruction or a data scanning instruction based on whether a cache apparatus of the table data processing node caches the read row data, and sends the data rescanning instruction or the data scanning instruction to a driven table scanning scheduling apparatus of the table data processing node. The driven table scanning scheduling apparatus obtains a driven table data query result based on the data rescanning instruction or the data scanning instruction, and returns the driven table data query result to the table data query apparatus.

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

Abstract: A method includes constructing a set of reference design contents associated with a set of reference design recipes. The method also includes determining a content similarity between a user design content and a reference design content taken from the set of reference design contents. The method further includes executing a design flow specified by a reference design recipe associated with the reference design content, as a result of the content similarity reaching a predetermined threshold.

Abstract: A device is disclosed. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed. A first width of at least one first metal interconnect is different from a second width of one of the plurality of second metal interconnects.

Abstract: A clock distribution system includes a clock mesh structure which has first metal patterns extending along a first axis, second metal patterns extending along a second axis, third metal patterns extending along a third axis. The first metal patterns, second metal patterns, and third metal patterns are electrically coupled with each other. The second axis is transverse to the first axis. The third axis is oblique to both the first axis and the second axis. The first metal patterns include a main first metal pattern, and other first metal patterns. The second metal patterns include a main second metal pattern, and other second metal patterns. The third metal patterns include a main third metal pattern, and other third metal patterns.

Abstract: A method includes: providing a first layout of a first layer over a substrate, the first layer having at least one metal pattern, and generating a second layout by placing a cut mask at a first position relative to the substrate to remove material from a first region of the at least one metal pattern to provide a first metal pattern and placing the cut mask at a second position relative to the first layer over the substrate to remove material from a second region of the at least one metal pattern to provide a second metal pattern.

Abstract: A method in certain embodiments includes using a computer system that includes an EDA tool to generate a layout of an IC device; searching, using a statistical method such as Bayesian optimization process, for one or more input variable parameters, such as the dimensions of the IC device and the dimensions of the voltage areas in the IC device, that results in an optimal characteristic, such as power, performance or area (PPA) of the IC device, subject to a limiting condition, such as one determined using a cost function. A computer system including one or more EDAs configured to perform the method is also disclosed.

Abstract: The routing of conductors in the conductor layers in an integrated circuit are routed using mixed-Manhattan-diagonal routing. Various techniques are disclosed for selecting a conductor scheme for the integrated circuit prior to fabrication of the integrated circuit. Techniques are also disclosed for determining the supply and/or the demand for the edges in the mixed-Manhattan-diagonal routing.

Abstract: A switching converter circuit for switching one end of an inductor therein between plural voltages according to a pulse width modulation (PWM) signal to convert an input voltage to an output voltage. The switching converter circuit has a driver circuit including a high side driver, a low side driver, a high side sensor circuit, and a low side sensor circuit. The high side sensor circuit is configured to sense a gate-source voltage of a high side metal oxide semiconductor field effect transistor (MOSFET), to generate a low side enable signal for enabling the low side driver to switch a low side MOSFET according to the PWM signal. The low side sensor circuit is configured to sense a gate-source voltage of a low side MOSFET, to generate a high side enable signal for enabling the high side driver to switch a high side MOSFET according to the PWM signal.