Abstract: A portable quantification apparatus for assessing joint accessory movement is disclosed in the present invention. The apparatus includes a reference unit, a movement unit, a sliding unit and a displacement sensor. The reference unit has a first probe and a first force sensor. The movement unit has a second probe and a second force sensor. The sliding unit is disposed between the reference unit and the movement unit which allows the movement unit to slide alongside with the reference unit. When a patient is under a test, the first probe is against one of two adjacent bones of a joint, while the second probe is against the other adjacent bone. The first force sensor and the second force sensor sense a first force and a second force applying to the reference unit and the movement unit respectively. The displacement sensor measures a relative movement of the movement unit over the reference unit.

Abstract: A method of controlling a battery-powered remote controller to decrease a duty cycle to allow continued operations despite the quantity of the battery is bad determines a drop in voltage of the battery in standby mode as voltage of the battery is being read. When receiving a command to activate a voice function, determining whether the drop in voltage in standby mode is greater than or equal to a preset value. If yes, the method then determines whether the drop in voltage falls in a preset range. If yes, the method regulates a duty cycle of the pulse signal activating the voice function, and activates the voice function as required. A remote controller and a non-transitory storage medium are also provided.

Abstract: A high voltage device includes: a semiconductor layer, a well, a body region, a gate, a source, a drain, and a drift oxide region. The semiconductor layer is formed on a substrate, wherein the semiconductor layer has at least one trench. The well is formed in the semicoducotor layer. The body region is formed in the well. The gate is formed on the well, and is in contact with the well. The source and the drain are located below, outside, and at different sides of the gate, in the body region and the well respectively. The drift oxide region is formed on a drift region, wherein a bottom surface of the drift oxide region is higher than a bottom surface of the trench.

Abstract: A high voltage device for use as an up-side switch of a power stage circuit includes: at least one lateral diffused metal oxide semiconductor (LDMOS) device, a second conductivity type isolation region and at least one Schottky barrier diode (SBD). The LDMOS device includes: a well formed in a semiconductor layer, a body region, a gate, a source and a drain. The second conductivity type isolation region is formed in the semiconductor layer and is electrically connected to the body region. The SBD includes: a Schottky metal layer formed on the semiconductor layer and a Schottky semiconductor layer formed in the semiconductor layer. The Schottky semiconductor layer and the Schottky metal layer form a Schottky contact. In the semiconductor layer, the Schottky semiconductor layer is adjacent to and in contact with the second conductivity type isolation region.

Abstract: Transparent end-to-end freight management is disclosed. A system for transparent end-to-end freight management can include carrier devices, cargo endpoint devices, teleconnected containers, a container and transport parameter provisional allocation engine, a transparent container and transport parameter disposition engine, a freight forwarding oversight engine, a container maintenance engine, and national customs office devices. The system can also include a carrier datastore, a shipper datastore, a recipient datastore, a container datastore, a third party datastore, a mode/route datastore, a contract datastore, a transport state datastore, a container state datastore, and a third party state datastore.

Abstract: A method for manufacturing a semiconductor device is provided. The method comprises determining a dimensional quantity of a layout pattern having an angle relative to grid lines of a minimum grid. The minimum grid may be defined by a first quantity associated with a first direction and a second quantity associated with a second direction perpendicular to the first direction. The determination of the dimensional quantity of the layout pattern is based on the first quantity, the second quantity and the angle of the layout pattern relative to the grid lines of the minimum grid.

Abstract: The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a first device, first electrical connectors, a second device and second electrical connectors. The first device is attached to a package substrate. An active side of the first device die faces toward the package substrate. The first electrical connectors connect the active side of the first device die to the package substrate. The second device die is stacked over the first device die. An active side of the second device die faces toward the package substrate. A portion of the active side of the second device die is outside an area that overlaps the first device die. The second electrical connectors connect the portion of the active side of the second device die to the package substrate.

Abstract: A method, includes: extracting a design data using a computer, wherein the design data includes a net name and a connective layer name of each layout design in each cell; generating a layout pattern corresponding to the design data by assigning an ID to said each layout design, wherein the ID includes a first indicator indicative of the net name and a second indicator indicative of the connective layer name; and checking the layout pattern to locate an error of the layout pattern.

Abstract: The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a package substrate, a bottom device die, an interposing package substrate and a top device die. The bottom device die is bonded to the package substrate. The interposing package substrate is located over the bottom device die and bonded to the package substrate. The top device die is bonded to the interposing package substrate form above the interposing package substrate.

Abstract: The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a first device, first electrical connectors, a second device and second electrical connectors. The first device is attached to a package substrate. An active side of the first device die faces toward the package substrate. The first electrical connectors connect the active side of the first device die to the package substrate. The second device die is stacked over the first device die. An active side of the second device die faces toward the package substrate. A portion of the active side of the second device die is outside an area that overlaps the first device die. The second electrical connectors connect the portion of the active side of the second device die to the package substrate.

Abstract: Disclosed is a toy device with a visual dislocation effect, which includes: a chassis; a wheel group, mounted on the chassis; a displacement driving motor group, mounted on the chassis and configured to drive the wheel group to move so as to drive the chassis to move and turn; a rotating driving motor, mounted on the chassis; a vehicle housing, covering above the chassis and separated from the chassis; and a transmission mechanism, connected to the rotating driving motor and the vehicle housing, wherein under the driving of the rotating driving motor, the transmission mechanism drives the vehicle housing to rotate relative to the chassis. According to the toy vehicle, the visual dislocation effect can be achieved; and the entertainment is greatly improved.

Abstract: A method includes: obtaining, by an inner table node that stores a portion of an inner table, a portion of an outer table from each of outer table nodes, and wherein a size of the outer table is less than a size of the inner table; reading, by the inner table node, the outer table by table joining threads or table joining processes of the inner table node; matching, by the table joining threads or the table joining processes, the outer table with the portion of the inner table stored at the inner table node; and outputting, by the inner table node, data from the outer table and the portion of the inner table that matches with each other.

Abstract: A high voltage device includes: a crystalline silicon layer, a well, a body region, a gate, a source, and a drain. The body region has a P-type conductivity type, and is formed in the well. The gate is located on and in contact with the well. The source and the drain have an N-type conductivity type, and are located below, outside, and at different sides of the gate, and are located in the body region and the well respectively. An inverse region is defined in the body region between the source and the well, to serve as an inverse current channel in an ON operation. The inverse region includes a germanium distribution region which has a germanium atom concentration higher than 1*1013 atoms/cm2. Adrift region is defined in the well, between the body region and the drain, to serve as a drift current channel in an ON operation.

Abstract: A device is disclosed. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed. A first via connects the first metal interconnect to the pin, and the at least one first metal interconnect is perpendicular to the pin.

Abstract: A chip-package device includes a substrate, a first chip, a first conductive layer, first wirings, and second wirings. The substrate includes a first top surface and first connection pads disposed on the first top surface. The first chip is disposed on the first top surface, and the first chip includes a second top surface and second connection pads disposed on the second top surface. The first conductive layer is disposed on the second top surface. The first wirings connect the first connection pads and the first conductive layer, and the second wirings connect the second connection pads and another side of the first conductive layer. Each of the first wirings and each of the second wirings respectively connect opposite sides of the first conductive layer.

Abstract: A method, includes: extracting a design data using a computer, wherein the design data includes a net name and a connective layer name of each layout design in each cell; generating a layout pattern corresponding to the design data by assigning an ID to said each layout design, wherein the ID includes a first indicator indicative of the net name and a second indicator indicative of the connective layer name; and checking the layout pattern to locate an error of the layout pattern.

Abstract: The present invention provides a high voltage device and a manufacturing method thereof. The high voltage device includes: a semiconductor layer, a drift oxide region, a well, a body region, a gate, at least one sub-gate, a source, and a drain. The drift oxide region is located on a drift region in an operation region. The sub-gate is formed on the drift oxide region right above the drift region. The sub-gate is parallel with the gate. A conductive layer of the gate has a first conductivity type, and a conductive layer of the sub-gate has a second conductivity type or is an intrinsic semiconductor structure.

Abstract: A device is disclosed that includes a cell block, at least one first metal interconnect, and second metal interconnects. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The at least one first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the at least one first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the at least one first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed.

Abstract: A high voltage device includes: a crystalline silicon layer, a well, a body region, a gate, a source, and a drain. The body region has a P-type conductivity type, and is formed in the well. The gate is located on and in contact with the well. The source and the drain have an N-type conductivity type, and are located below, outside, and at different sides of the gate, and are located in the body region and the well respectively. An inverse region is defined in the body region between the source and the well, to serve as an inverse current channel in an ON operation. The inverse region includes a germanium distribution region which has a germanium atom concentration higher than 1*1013 atoms/cm2. Adrift region is defined in the well, between the body region and the drain, to serve as a drift current channel in an ON operation.

Abstract: A method of controlling a battery-powered remote controller to decrease a duty cycle to allow continued operations despite the quantity of the battery is bad determines a drop in voltage of the battery in standby mode as voltage of the battery is being read. When receiving a command to activate a voice function, determining whether the drop in voltage in standby mode is greater than or equal to a preset value. If yes, the method then determines whether the drop in voltage falls in a preset range. If yes, the method regulates a duty cycle of the pulse signal activating the voice function, and activates the voice function as required. A remote controller and a non-transitory storage medium are also provided.