Patents by Inventor Huanlong Liu

Huanlong Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10522752
    Abstract: A perpendicularly magnetized magnetic tunnel junction (p-MTJ) is disclosed wherein a boron containing free layer (FL) is subjected to a plasma treatment with inert gas, and a natural oxidation (NOX) process to form B2O3 before overlying layers are deposited. A metal layer such as Mg is deposited on the FL as a first step in forming a Hk enhancing layer that increases FL perpendicular magnetic anisotropy, or as a first step in forming a tunnel barrier layer on the FL. One or more anneal steps are essential in assisting B2O3 segregation from the free layer and thereby increasing the FL magnetic moment. A post-oxidation plasma treatment may also be used to partially remove B2O3 proximate to the FL top surface before the metal layer is deposited. Both plasma treatments use low power (<50. Watts) to remove a maximum of 2. Angstroms FL thickness.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guenole Jan, Jodi Mari Iwata, Ru-Ying Tong, Huanlong Liu, Yuan-Jen Lee, Jian Zhu
  • Patent number: 10522747
    Abstract: A laminated seed layer stack with a smooth top surface having a peak to peak roughness of 0.5 nm is formed by sequentially sputter depositing a first seed layer, a first amorphous layer, a second seed layer, and a second amorphous layer where each seed layer may be Mg and has a resputtering rate 2 to 30X that of the amorphous layers that are TaN, SiN, or a CoFeM alloy. A template layer that is NiCr or NiFeCr is formed on the second amorphous layer. As a result, perpendicular magnetic anisotropy in an overlying magnetic layer that is a reference layer, free layer, or dipole layer is substantially maintained during high temperature processing up to 400° C. and is advantageous for magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. The laminated seed layer stack may include a bottommost Ta or TaN buffer layer.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACUTING COMPANY, LTD.
    Inventors: Jian Zhu, Guenole Jan, Yuan-Jen Lee, Huanlong Liu, Ru-Ying Tong, Po-Kang Wang
  • Patent number: 10522745
    Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein a free layer (FL) interfaces with a first metal oxide (Mox) layer and second metal oxide (tunnel barrier) to produce perpendicular magnetic anisotropy (PMA) in the FL. In some embodiments, conductive metal channels made of a noble metal are formed in the Mox that is MgO to reduce parasitic resistance. In a second embodiment, a discontinuous MgO layer with a plurality of islands is formed as the Mox layer and a non-magnetic hard mask layer is deposited to fill spaces between adjacent islands and form shorting pathways through the Mox. In another embodiment, end portions between the sides of a center Mox portion and the MTJ sidewall are reduced to form shorting pathways by depositing a reducing metal layer on Mox sidewalls, or performing a reduction process with forming gas, H2, or a reducing species.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sahil Patel, Guenole Jan, Ru-Ying Tong, Vignesh Sundar, Dongna Shen, Yu-Jen Wang, Po-Kang Wang, Huanlong Liu
  • Patent number: 10509074
    Abstract: A stimulus/response controller within a magnetic electrical test apparatus is configured for generating and transmitting stimulus waveforms to a high-speed DAC for application to a MTJ DUT. The response signal from the MTJ DUT is applied to an ADC that digitizes and transfers the response signal to the stimulus/response controller. The stimulus/response controller has a configurable function circuit that is selectively configured for performing evaluation and analysis of the digitized stimulus and response signals. The configurable functions are structured for performing any evaluation and analysis function for determining the characteristics of the MTJ DUT(s). Examples of the evaluation and analysis operations include averaging the stimulus and/or response signals, determining the differential resistance, the degradation times, failure counts, or the bit error rate of the MTJ DUT(s).
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guenole Jan, Huanlong Liu, Jian Zhu, Yuan-Jen Lee, Po-Kang Wang
  • Publication number: 20190311754
    Abstract: An initialization process is disclosed for a perpendicular magnetic tunnel junction (p-MTJ) wherein the switching error rate is reduced from a typical range of 30-100 ppm to less than 10 ppm. In one embodiment, an in-plane magnetic field is applied after a final anneal step is performed during memory device fabrication such that all magnetizations in the free layer, and AP1 and AP2 pinned layers are temporarily aligned “in-plane”. After the applied field is removed, interfacial perpendicular magnetic anisotropy (PMA) at a tunnel barrier/AP1 interface induces a single AP1 magnetic domain with a magnetization in a first vertical direction. Interfacial PMA at a FL/tunnel barrier interface affords a single FL domain with magnetization in the first direction or opposite thereto. AP2 magnetization is opposite to the first direction as a result of antiferromagnetic coupling with the AP1 layer. Alternatively, a perpendicular-to-plane magnetic field may be applied for initialization.
    Type: Application
    Filed: June 17, 2019
    Publication date: October 10, 2019
    Inventors: Yuan-Jen Lee, Guenole Jan, Huanlong Liu, Jian Zhu
  • Patent number: 10431736
    Abstract: A magnetic tunnel junction with perpendicular magnetic anisotropy (PMA MTJ) is disclosed wherein a free layer interfaces with a tunnel barrier and has a second interface with an oxide layer. A lattice-matching layer adjoins an opposite side of the oxide layer with respect to the free layer and is comprised of CoXFeYNiZLWMV or an oxide or nitride of Ru, Ta, Ti, or Si, wherein L is one of B, Zr, Nb, Hf, Mo, Cu, Cr, Mg, Ta, Ti, Au, Ag, or P, and M is one of Mo, Mg, Ta, Cr, W, or V, (x+y+z+w+v)=100 atomic %, x+y>0, and each of v and w are >0. The lattice-matching layer grows a BCC structure during annealing thereby promoting BCC structure growth in the oxide layer that results in enhanced free layer PMA and improved thermal stability.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: October 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huanlong Liu, Yuan-Jen Lee, Jian Zhu, Guenole Jan, Luc Thomas, Po-Kang Wang, Ru-Ying Tong, Jodi Mari Iwata
  • Publication number: 20190257881
    Abstract: A stimulus/response controller within a magnetic electrical test apparatus is configured for generating and transmitting stimulus waveforms to a high-speed DAC for application to a MTJ DUT. The response signal from the MTJ DUT is applied to an ADC that digitizes and transfers the response signal to the stimulus/response controller. The stimulus/response controller has a configurable function circuit that is selectively configured for performing evaluation and analysis of the digitized stimulus and response signals. The configurable functions are structured for performing any evaluation and analysis function for determining the characteristics of the MTJ DUT(s). Examples of the evaluation and analysis operations include averaging the stimulus and/or response signals, determining the differential resistance, the degradation times, failure counts, or the bit error rate of the MTJ DUT(s).
    Type: Application
    Filed: February 22, 2018
    Publication date: August 22, 2019
    Inventors: Guenole Jan, Huanlong Liu, Jian Zhu, Yuan-Jen Lee, Po-Kang Wang
  • Publication number: 20190237661
    Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein first and second interfaces of a free layer (FL) with a first metal oxide (Hk enhancing layer) and second metal oxide (tunnel barrier), respectively, produce perpendicular magnetic anisotropy (PMA) to increase thermal stability. In some embodiments, a capping layer that is a conductive metal nitride such as MoN contacts an opposite surface of the Hk enhancing layer with respect to the first interface to reduce interdiffusion of oxygen and nitrogen compared with a TiN capping layer and maintain an acceptable resistance×area (RA) product. In other embodiments, the capping layer may comprise an insulating nitride such as AlN that is alloyed with a conductive metal to minimize RA. Furthermore, a metallic buffer layer may be inserted between the capping layer and Hk enhancing layer. As a result, electrical shorts are reduced and the magnetoresistive ratio is increased.
    Type: Application
    Filed: January 26, 2018
    Publication date: August 1, 2019
    Inventors: Jodi Mari Iwata, Guenole Jan, Ru-Ying Tong, Vignesh Sundar, Jian Zhu, Huanlong Liu
  • Publication number: 20190189910
    Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein a free layer (FL) interfaces with a first metal oxide (Mox) layer and second metal oxide (tunnel barrier) to produce perpendicular magnetic anisotropy (PMA) in the FL. In some embodiments, conductive metal channels made of a noble metal are formed in the Mox that is MgO to reduce parasitic resistance. In a second embodiment, a discontinuous MgO layer with a plurality of islands is formed as the Mox layer and a non-magnetic hard mask layer is deposited to fill spaces between adjacent islands and form shorting pathways through the Mox. In another embodiment, end portions between the sides of a center Mox portion and the MTJ sidewall are reduced to form shorting pathways by depositing a reducing metal layer on Mox sidewalls, or performing a reduction process with forming gas, H2, or a reducing species.
    Type: Application
    Filed: December 14, 2017
    Publication date: June 20, 2019
    Inventors: Sahil Patel, Guenole Jan, Ru-Ying Tong, Vignesh Sundar, Dongna Shen, Yu-Jen Wang, Po-Kang Wang, Huanlong Liu
  • Publication number: 20190189911
    Abstract: A laminated seed layer stack with a smooth top surface having a peak to peak roughness of 0.5 nm is formed by sequentially sputter depositing a first seed layer, a first amorphous layer, a second seed layer, and a second amorphous layer where each seed layer may be Mg and has a resputtering rate 2 to 30X that of the amorphous layers that are TaN, SiN, or a CoFeM alloy. A template layer that is NiCr or NiFeCr is formed on the second amorphous layer. As a result, perpendicular magnetic anisotropy in an overlying magnetic layer that is a reference layer, free layer, or dipole layer is substantially maintained during high temperature processing up to 400° C. and is advantageous for magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. The laminated seed layer stack may include a bottommost Ta or TaN buffer layer.
    Type: Application
    Filed: February 19, 2019
    Publication date: June 20, 2019
    Inventors: Jian Zhu, Guenole Jan, Yuan-Jen Lee, Huanlong Liu, Ru-Ying Tong, Po-Kang Wang
  • Patent number: 10325639
    Abstract: An initialization process is disclosed for a perpendicular magnetic tunnel junction (p-MTJ) wherein the switching error rate is reduced from a typical range of 30-100 ppm to less than 10 ppm. In one embodiment, an in-plane magnetic field is applied after a final anneal step is performed during memory device fabrication such that all magnetizations in the free layer, and AP1 and AP2 pinned layers are temporarily aligned “in-plane”. After the applied field is removed, interfacial perpendicular magnetic anisotropy (PMA) at a tunnel barrier/AP1 interface induces a single AP1 magnetic domain with a magnetization in a first vertical direction. Interfacial PMA at a FL/tunnel barrier interface affords a single FL domain with magnetization in the first direction or opposite thereto. AP2 magnetization is opposite to the first direction as a result of antiferromagnetic coupling with the AP1 layer. Alternatively, a perpendicular-to-plane magnetic field may be applied for initialization.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: June 18, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Jen Lee, Guenole Jan, Huanlong Liu, Jian Zhu
  • Publication number: 20190156876
    Abstract: An initialization process is disclosed for a perpendicular magnetic tunnel junction (p-MTJ) wherein the switching error rate is reduced from a typical range of 30-100 ppm to less than 10 ppm. In one embodiment, an in-plane magnetic field is applied after a final anneal step is performed during memory device fabrication such that all magnetizations in the free layer, and AP1 and AP2 pinned layers are temporarily aligned “in-plane”. After the applied field is removed, interfacial perpendicular magnetic anisotropy (PMA) at a tunnel barrier/AP1 interface induces a single AP1 magnetic domain with a magnetization in a first vertical direction. Interfacial PMA at a FL/tunnel barrier interface affords a single FL domain with magnetization in the first direction or opposite thereto. AP2 magnetization is opposite to the first direction as a result of antiferromagnetic coupling with the AP1 layer. Alternatively, a perpendicular-to-plane magnetic field may be applied for initialization.
    Type: Application
    Filed: November 20, 2017
    Publication date: May 23, 2019
    Inventors: Yuan-Jen Lee, Guenole Jan, Huanlong Liu, Jian Zhu
  • Publication number: 20190140168
    Abstract: A seed layer stack with a uniform top surface having a peak to peak roughness of 0.5 nm is formed by sputter depositing an amorphous layer on a smoothing layer such as Mg where the latter has a resputtering rate 2 to 30× that of the amorphous layer. The uppermost seed (template) layer is NiW, NiMo, or one or more of NiCr, NiFeCr, and Hf while the bottommost seed layer is one or more of Ta, TaN, Zr, ZrN, Nb, NbN, Mo, MoN, TiN, W, WN, and Ru. Accordingly, perpendicular magnetic anisotropy in an overlying magnetic layer is substantially maintained during high temperature processing up to 400° C. and is advantageous for magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. The amorphous seed layer is SiN, TaN, or CoFeM where M is B or another element with a content that makes CoFeM amorphous as deposited.
    Type: Application
    Filed: December 17, 2018
    Publication date: May 9, 2019
    Inventors: Jian Zhu, Guenole Jan, Yuan-Jen Lee, Huanlong Liu, Ru-Ying Tong, Jodi Mari Iwata, Vignesh Sundar, Luc Thomas, Yu-Jen Wang, Sahil Patel
  • Publication number: 20190109277
    Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein a free layer (FL) interfaces with a metal oxide (Mox) layer and a tunnel barrier layer to produce interfacial perpendicular magnetic anisotropy (PMA). The Mox layer has a non-stoichiometric oxidation state to minimize parasitic resistance, and comprises a dopant to fill vacant lattice sites thereby blocking oxygen diffusion through the Mox layer to preserve interfacial PMA and high thermal stability at process temperatures up to 400° C. Various methods of forming the doped Mox layer include deposition of the M layer in a reactive environment of O2 and dopant species in gas form, exposing a metal oxide layer to dopant species in gas form, and ion implanting the dopant. In another embodiment, where the dopant is N, a metal nitride layer is formed on a metal oxide layer, and then an anneal step drives nitrogen into vacant sites in the metal oxide lattice.
    Type: Application
    Filed: October 10, 2017
    Publication date: April 11, 2019
    Inventors: Guenole Jan, Jodi Mari Iwata, Ru-Ying Tong, Huanlong Liu, Yuan-Jen Lee, Jian Zhu
  • Publication number: 20190088866
    Abstract: A seed layer stack with a uniform top surface having a peak to peak roughness of 0.5 nm is formed by sputter depositing an amorphous layer on a smoothing layer such as Mg where the latter has a resputtering rate 2 to 30× that of the amorphous layer. The seed layer stack may be repeated to give a laminate of two amorphous layers and two smoothing layers, and is advantageous for enhancing performance in magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. A template layer such as NiCr may be formed on the uppermost smoothing layer to promote and maintain perpendicular magnetic anisotropy in an overlying magnetic layer during high temperature processing up to 400° C. The amorphous seed layer is SiN, TaN, or CoFeM where M is B or another element with a content that makes CoFeM amorphous as deposited.
    Type: Application
    Filed: October 29, 2018
    Publication date: March 21, 2019
    Inventors: Jian Zhu, Guenole Jan, Yuan-Jen Lee, Huanlong Liu, Ru-Ying Tong, Jodi Mari Iwata, Vignesh Sundar, Luc Thomas, Yu-Jen Wang, Sahil Patel
  • Patent number: 10230044
    Abstract: A laminated seed layer stack with a smooth top surface having a peak to peak roughness of 0.5 nm is formed by sequentially sputter depositing a first seed layer, a first amorphous layer, a second seed layer, and a second amorphous layer where each seed layer may be Mg and has a resputtering rate 2 to 30× that of the amorphous layers that are TaN, SiN, or a CoFeM alloy. A template layer that is NiCr or NiFeCr is formed on the second amorphous layer. As a result, perpendicular magnetic anisotropy in an overlying magnetic layer that is a reference layer, free layer, or dipole layer is substantially maintained during high temperature processing up to 400° C. and is advantageous for magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. The laminated seed layer stack may include a bottommost Ta or TaN buffer layer.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: March 12, 2019
    Assignee: Headway Technologies, Inc.
    Inventors: Jian Zhu, Guenole Jan, Yuan-Jen Lee, Huanlong Liu, Ru-Ying Tong, Po-Kang Wang
  • Publication number: 20180358071
    Abstract: Circuits and methods for programming a MTJ stack of an MRAM cell minimizes a ferromagnetic free layer or pinned layer polarization reversal due to back-hopping. The programming begins by applying a first segment of the segment of the write pulse at a first write voltage level for a first time period to program the MTJ stack. A second segment of the segment of the write pulse at a second write voltage level that is less than the first write voltage level is applied to the magnetic tunnel junction stack for a second time period to correct the polarization of the MTJ when the MTJ stack has reversed polarization during the first time period. The second segment of the segment of the write pulse may be a ramp, or multiple ramps, or have a quiescent period between it and the first segment of the write pulse.
    Type: Application
    Filed: June 7, 2017
    Publication date: December 13, 2018
    Inventors: Huanlong Liu, Guenole Jan, Yuan-Jen Lee, Jian Zhu, Po-Kang Wang
  • Publication number: 20180323371
    Abstract: A magnetic tunnel junction with perpendicular magnetic anisotropy (PMA MTJ) is disclosed wherein a free layer interfaces with a tunnel barrier and has a second interface with an oxide layer. A lattice-matching layer adjoins an opposite side of the oxide layer with respect to the free layer and is comprised of CoXFeYNiZLWMV or an oxide or nitride of Ru, Ta, Ti, or Si, wherein L is one of B, Zr, Nb, Hf, Mo, Cu, Cr, Mg, Ta, Ti, Au, Ag, or P, and M is one of Mo, Mg, Ta, Cr, W, or V, (x+y+z+w+v)=100 atomic %, x+y>0, and each of v and w are >0. The lattice-matching layer grows a BCC structure during annealing thereby promoting BCC structure growth in the oxide layer that results in enhanced free layer PMA and improved thermal stability.
    Type: Application
    Filed: June 29, 2018
    Publication date: November 8, 2018
    Inventors: Huanlong Liu, Yuan-Jen Lee, Jian Zhu, Guenole Jan, Luc Thomas, Po-Kang Wang, Ru-Ying Tong, Jodi Mari Iwata
  • Patent number: 10115892
    Abstract: A seed layer stack with a uniform top surface having a peak to peak roughness of 0.5 nm is formed by sputter depositing an amorphous layer on a smoothing layer such as Mg where the latter has a resputtering rate 2 × to 30 × that of the amorphous layer. The uppermost seed (template) layer is NiW, NiMo, or one or more of NiCr, NiFeCr, and Hf while the bottommost seed layer is Ta or TaN, for example. Accordingly, perpendicular magnetic anisotropy in an overlying magnetic layer is maintained during high temperature processing up to 400° C. and is advantageous for magnetic tunnel junctions in embedded memory devices, or read head sensors. The amorphous seed layer is SiN, TaN, or CoFeM where M may be B.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: October 30, 2018
    Assignee: Headway Technologies, Inc.
    Inventors: Jian Zhu, Guenole Jan, Yuan-Jen Lee, Huanlong Liu, Ru-Ying Tong, Jodi Mari Iwata, Vignesh Sundar, Luc Thomas, Yu-Jen Wang, Sahil Patel
  • Patent number: 10014465
    Abstract: A magnetic tunnel junction with perpendicular magnetic anisotropy (PMA MTJ) is disclosed wherein a free layer has an interface with a tunnel barrier and a second interface with an oxide layer. A lattice-matching layer adjoins an opposite side of the oxide layer with respect to the free layer and is comprised of CoXFeYNiZLWMV or CoXFeYNiZLW wherein L is one of B, Zr, Nb, Hf, Mo, Cu, Cr, Mg, Ta, Ti, Au, Ag, or P, and M is one of Mo, Mg, Ta, Cr, W, or V, (x+y+z+w+v)=100 atomic %, x+y>0, and each of v and w are >0. The lattice-matching layer grows a BCC structure during annealing at about 400° C. thereby promoting BCC structure growth in the oxide layer. As a result, free layer PMA is enhanced and maintained to yield improved thermal stability.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: July 3, 2018
    Assignee: Headway Technologies, Inc.
    Inventors: Huanlong Liu, Yuan-Jen Lee, Jian Zhu, Guenole Jan, Luc Thomas, Po-Kang Wang, Ru-Ying Tong, Jodi Mari Iwata