Patents by Inventor Huanzhang Huang
Huanzhang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10763841Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.Type: GrantFiled: August 8, 2019Date of Patent: September 1, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Huanzhang Huang, Amit Rane
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Publication number: 20200272590Abstract: Aspects of the disclosure provide for a method. In at least some examples, the method includes receiving, at a circuit, data via a differential input signal. The method further includes detecting a falling edge in the data received via the differential input signal. The method further includes holding an output of the circuit at a final logical value of the data. The method further includes disabling a transmitter of the circuit while holding the output of the circuit at the final logical value of the data. The method further includes releasing the output of the circuit from the final logical value of the data.Type: ApplicationFiled: May 14, 2020Publication date: August 27, 2020Inventors: Win Naing MAUNG, Bhupendra SHARMA, Huanzhang HUANG, Douglas Edward WENTE, Suzanne Mary VINING, Mustafa Ulvi ERDOGAN
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Publication number: 20200242071Abstract: A serial bus signal conditioner circuit includes receiver circuitry, a mode identification circuit, and an edge-rate booster circuit. The receiver circuitry is configured to receive signals transmitted on a serial bus. The mode identification circuit is coupled to the receiver circuitry, and is configured to identify initiation of or return to high-speed signaling on the serial bus based on sequences of the signals transmitted on the serial bus. The edge-rate booster circuit is coupled to the mode identification circuit, and is configured to identify edges of a differential signal transmitted on the serial bus, and to supply a differential current to the serial bus based on identification of an edge of the differential signal.Type: ApplicationFiled: January 24, 2020Publication date: July 30, 2020Inventors: Win Naing MAUNG, Suzanne Mary VINING, Yonghui TANG, Douglas Edward WENTE, Huanzhang HUANG
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Publication number: 20200204165Abstract: Aspects of the disclosure provide for a method. In some examples, the method includes detecting a transition in an input signal (IN), generating a bias current based on the detected transition in IN, and modifying a charge status of a capacitor based on the charge current. The method further includes generating an output signal (OUT) based on the charge status of the capacitor, disabling the bias current generation based on values of IN and OUT, and strongly pulling the capacitor up or down based on the disabling the bias current generation.Type: ApplicationFiled: February 28, 2020Publication date: June 25, 2020Inventors: Yanfei JIANG, Huanzhang HUANG, Yonghui TANG, Shita GUO
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Patent number: 10657089Abstract: Aspects of the disclosure provide for a method. In at least some examples, the method includes receiving, at a circuit, data via a differential input signal. The method further includes detecting a falling edge in the data received via the differential input signal. The method further includes holding an output of the circuit at a final logical value of the data. The method further includes disabling a transmitter of the circuit while holding the output of the circuit at the final logical value of the data. The method further includes releasing the output of the circuit from the final logical value of the data.Type: GrantFiled: May 6, 2019Date of Patent: May 19, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Win Naing Maung, Bhupendra Sharma, Huanzhang Huang, Douglas Edward Wente, Suzanne Mary Vining, Mustafa Ulvi Erdogan
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Patent number: 10657090Abstract: Aspects of the disclosure provide for a method. In at least some examples, the method includes receiving, at a circuit, data via a differential input signal. The method further includes detecting a falling edge in the data received via the differential input signal. The method further includes holding an output of the circuit at a final logical value of the data. The method further includes disabling a transmitter of the circuit while holding the output of the circuit at the final logical value of the data. The method further includes releasing the output of the circuit from the final logical value of the data.Type: GrantFiled: December 17, 2019Date of Patent: May 19, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Win Naing Maung, Bhupendra Sharma, Huanzhang Huang, Douglas Edward Wente, Suzanne Mary Vining, Mustafa Ulvi Erdogan
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Publication number: 20200125517Abstract: Aspects of the disclosure provide for a method. In at least some examples, the method includes receiving, at a circuit, data via a differential input signal. The method further includes detecting a falling edge in the data received via the differential input signal. The method further includes holding an output of the circuit at a final logical value of the data. The method further includes disabling a transmitter of the circuit while holding the output of the circuit at the final logical value of the data. The method further includes releasing the output of the circuit from the final logical value of the data.Type: ApplicationFiled: December 17, 2019Publication date: April 23, 2020Inventors: Win Naing MAUNG, Bhupendra SHARMA, Huanzhang HUANG, Douglas Edward WENTE, Suzanne Mary VINING, Mustafa Ulvi ERDOGAN
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Patent number: 10622979Abstract: Aspects of the disclosure provide for a method. In some examples, the method includes detecting a transition in an input signal (IN), generating a bias current based on the detected transition in IN, and modifying a charge status of a capacitor based on the charge current. The method further includes generating an output signal (OUT) based on the charge status of the capacitor, disabling the bias current generation based on values of IN and OUT, and strongly pulling the capacitor up or down based on the disabling the bias current generation.Type: GrantFiled: March 28, 2019Date of Patent: April 14, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yanfei Jiang, Huanzhang Huang, Yonghui Tang, Shita Guo
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Publication number: 20200112302Abstract: In examples, an integrated circuit package comprises a pin exposed externally to the package; at least one resistor coupled to the pin at a first end of the resistor; a first transistor coupled to the at least one resistor at a second end of the resistor and coupled to a voltage source; a second transistor coupled to the at least one resistor at the second end of the resistor and coupled to a ground connection, the at least one resistor and the first and second transistors couple at a first node, the first and second transistors are of different types; and multiple comparators, each of the multiple comparators coupled to a voltage divider network and to the pin.Type: ApplicationFiled: December 5, 2019Publication date: April 9, 2020Inventors: Huanzhang HUANG, Jikai CHEN, Yanli FAN, MD Anwar SADAT
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Publication number: 20200073839Abstract: Aspects of the disclosure provide for a circuit including a squelch detector having a first input coupled to a first node and configured to receive a positive component of a differential signal with a floating center tap, a second input coupled to a second node and configured to receive a negative component of the differential signal, and an output coupled to a logic circuit, a first resistor coupled between the first node and a third node, a second resistor coupled between the third node and the second node, a third resistor coupled between the first node and a fourth node, a fourth resistor coupled between the fourth node and the second node, a capacitor coupled between the fourth node and a ground terminal, a comparator having a first input coupled to the third node, a second input coupled to a fifth node, and an output coupled to the logic circuit.Type: ApplicationFiled: May 6, 2019Publication date: March 5, 2020Inventors: Win Naing MAUNG, Douglas Edward WENTE, Mustafa Ulvi ERDOGAN, Huanzhang HUANG, Saurabh GOYAL, Bhupendra SHARMA
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Publication number: 20200057742Abstract: Aspects of the present disclosure provide for a system. In at least some examples, the system includes an embedded Universal Serial Bus 2 (eUSB2) device having a first receiver and a first transmitter, a processor, a second transmitter coupled to the processor, a second receiver coupled to the processor, a drive low circuit coupled to the processor second transmitter, and differential signal lines having a length greater than ten inches. The differential signal lines are coupled at a first end to the first receiver and the first transmitter and at a second end to the second transmitter and the second receiver. The processor is configured to control the drive low circuit to drive the differential signal lines low with a logic ‘0’ to cause the first receiver to receive the logic ‘0’ and a value of a signal present on the differential signal lines to reach about 0 volts.Type: ApplicationFiled: May 16, 2019Publication date: February 20, 2020Inventors: Win Naing MAUNG, Yonghui TANG, Huanzhang HUANG, Douglas Edward WENTE
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Publication number: 20200059224Abstract: Aspects of the disclosure provide for a method. In some examples, the method includes detecting a transition in an input signal (IN), generating a bias current based on the detected transition in IN, and modifying a charge status of a capacitor based on the charge current. The method further includes generating an output signal (OUT) based on the charge status of the capacitor, disabling the bias current generation based on values of IN and OUT, and strongly pulling the capacitor up or down based on the disabling the bias current generation.Type: ApplicationFiled: March 28, 2019Publication date: February 20, 2020Inventors: Yanfei JIANG, Huanzhang HUANG, Yonghui TANG, Shita GUO
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Publication number: 20200052684Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.Type: ApplicationFiled: August 8, 2019Publication date: February 13, 2020Inventors: Huanzhang HUANG, Amit RANE
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Publication number: 20200042488Abstract: At least some aspects of the present disclosure provide for a method. In some examples, the method includes receiving, at a circuit, data via a differential input signal, detecting a rising edge in the data received via the differential input signal, and precharging a common mode voltage (Vcm) node of the differential input signal responsive to detecting the rising edge in the data received via the differential input signal, wherein the Vcm node is a floating node.Type: ApplicationFiled: May 6, 2019Publication date: February 6, 2020Inventors: Win Naing MAUNG, Saurabh GOYAL, Bhupendra SHARMA, Huanzhang HUANG, Douglas Edward WENTE, Suzanne Mary VINING, Mustafa Ulvi ERDOGAN
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Publication number: 20200034323Abstract: Aspects of the disclosure provide for a method. In at least some examples, the method includes receiving, at a circuit, data via a differential input signal. The method further includes detecting a falling edge in the data received via the differential input signal. The method further includes holding an output of the circuit at a final logical value of the data. The method further includes disabling a transmitter of the circuit while holding the output of the circuit at the final logical value of the data. The method further includes releasing the output of the circuit from the final logical value of the data.Type: ApplicationFiled: May 6, 2019Publication date: January 30, 2020Inventors: Win Naing MAUNG, Bhupendra SHARMA, Huanzhang HUANG, Douglas Edward WENTE, Suzanne Mary VINING, Mustafa Ulvi ERDOGAN
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Patent number: 10536138Abstract: In examples, an integrated circuit package comprises a pin exposed externally to the package; at least one resistor coupled to the pin at a first end of the resistor; a first transistor coupled to the at least one resistor at a second end of the resistor and coupled to a voltage source; a second transistor coupled to the at least one resistor at the second end of the resistor and coupled to a ground connection, the at least one resistor and the first and second transistors couple at a first node, the first and second transistors are of different types; and multiple comparators, each of the multiple comparators coupled to a voltage divider network and to the pin.Type: GrantFiled: September 13, 2018Date of Patent: January 14, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Huanzhang Huang, Jikai Chen, Yanli Fan, Md Anwar Sadat
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Patent number: 10394740Abstract: An apparatus includes a transistor with a control terminal, a first current terminal, and a second current terminal. The apparatus also includes a charge pump coupled to the control terminal of the transistor via a first and second paths. The first path comprises a first resistor and the second path comprises a second resistor in series with a diode. The first resistor has a higher resistance value than the second resistor.Type: GrantFiled: September 10, 2018Date of Patent: August 27, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shita Guo, Yanli Fan, Huanzhang Huang, Yonghui Tang, Yanfei Jiang
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Patent number: 10298238Abstract: A driver includes first and second resistors coupled to a supply voltage and coupled to pairs of main transistors at positive and negative output nodes. The first and second pairs of main transistors provide emphasis and de-emphasis on the positive and negative output nodes. The driver also includes a delay inverter, a pull up booster and a pull down booster. The delay inverter delays and inverts each of a pair of differential input signals to provide delayed and inverted differential signals. The pull up booster provides a bypass current path that bypasses the first and second resistors but includes at least some of the first and second pairs of main transistors. The pull down booster provides an additional current path from the supply voltage through the first or second resistor to ground.Type: GrantFiled: May 19, 2017Date of Patent: May 21, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Weicheng Zhang, Huanzhang Huang, Yanli Fan, Roland Sperlich
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Publication number: 20170257098Abstract: A driver includes first and second resistors coupled to a supply voltage and coupled to pairs of main transistors at positive and negative output nodes. The first and second pairs of main transistors provide emphasis and de-emphasis on the positive and negative output nodes. The driver also includes a delay inverter, a pull up booster and a pull down booster. The delay inverter delays and inverts each of a pair of differential input signals to provide delayed and inverted differential signals. The pull up booster provides a bypass current path that bypasses the first and second resistors but includes at least some of the first and second pairs of main transistors. The pull down booster provides an additional current path from the supply voltage through the first or second resistor to ground.Type: ApplicationFiled: May 19, 2017Publication date: September 7, 2017Inventors: Weicheng Zhang, Huanzhang Huang, Yanli Fan, Roland Sperlich
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Patent number: 9660652Abstract: A driver includes first and second resistors coupled to a supply voltage and coupled to pairs of main transistors at positive and negative output nodes. The first and second pairs of main transistors provide emphasis and de-emphasis on the positive and negative output nodes. The driver also includes a delay inverter, a pull up booster and a pull down booster. The delay inverter delays and inverts each of a pair of differential input signals to provide delayed and inverted differential signals. The pull up booster provides a bypass current path that bypasses the first and second resistors but includes at least some of the first and second pairs of main transistors. The pull down booster provides an additional current path from the supply voltage through the first or second resistor to ground.Type: GrantFiled: September 8, 2015Date of Patent: May 23, 2017Assignee: Texas Instruments IncorporatedInventors: Weicheng Zhang, Huanzhang Huang, Yanli Fan, Roland Sperlich