Abstract: A serial communication circuit (FIG. 3) is disclosed. The circuit includes an equalizer circuit (306) arranged to receive a data signal (CH 1) and produce an equalized data signal. A log detector circuit (300) receives the data signal and produces a power signal indicating a power level of the data signal. A decision circuit (332) receives the power signal and produces a select signal. A first selection circuit (336) receives a plurality of first correction signals and applies one of the first correction signals to the equalizer circuit in response to the select signal.

Abstract: A differential receiver with reduced common mode induced propagation delay variance. One implementation of a differential receiver includes a first differential amplifier, a second differential amplifier, and a first current source. The first differential amplifier includes a first transistor pair. The second differential amplifier includes a second transistor pair. The first current source is coupled to a drain node of a first transistor of the first transistor pair. The first current source is configured to generate a variable first current at the drain node as of function of a sum of a variable tail current of the first differential amplifier and a variable tail current of the second differential amplifier.

Abstract: A driver includes first and second resistors coupled to a supply voltage and coupled to pairs of main transistors at positive and negative output nodes. The first and second pairs of main transistors provide emphasis and de-emphasis on the positive and negative output nodes. The driver also includes a delay inverter, a pull up booster and a pull down booster. The delay inverter delays and inverts each of a pair of differential input signals to provide delayed and inverted differential signals. The pull up booster provides a bypass current path that bypasses the first and second resistors but includes at least some of the first and second pairs of main transistors. The pull down booster provides an additional current path from the supply voltage through the first or second resistor to ground.

Abstract: A serial communication circuit (FIG. 3) is disclosed. The circuit includes an equalizer circuit (306) arranged to receive a data signal (CH 1) and produce an equalized data signal. A log detector circuit (300) receives the data signal and produces a power signal indicating a power level of the data signal. A decision circuit (332) receives the power signal and produces a select signal. A first selection circuit (336) receives a plurality of first correction signals and applies one of the first correction signals to the equalizer circuit in response to the select signal.

Abstract: A serial communication circuit (FIG. 3) is disclosed. The circuit includes an equalizer circuit (306) arranged to receive a data signal (CH 1) and produce an equalized data signal. A log detector circuit (300) receives the data signal and produces a power signal indicating a power level of the data signal. A decision circuit (332) receives the power signal and produces a select signal. A first selection circuit (336) receives a plurality of first correction signals and applies one of the first correction signals to the equalizer circuit in response to the select signal.

Abstract: A serial communication circuit (FIG. 3) is disclosed. The circuit includes an equalizer circuit (306) arranged to receive a data signal (CH 1) and produce an equalized data signal. A log detector circuit (300) receives the data signal and produces a power signal indicating a power level of the data signal. A decision circuit (332) receives the power signal and produces a select signal. A first selection circuit (336) receives a plurality of first correction signals and applies one of the first correction signals to the equalizer circuit in response to the select signal.

Abstract: A differential receiver with reduced common mode induced propagation delay variance. One implementation of a differential receiver includes a first differential amplifier, a second differential amplifier, and a first current source. The first differential amplifier includes a first transistor pair. The second differential amplifier includes a second transistor pair. The first current source is coupled to a drain node of a first transistor of the first transistor pair. The first current source is configured to generate a variable first current at the drain node as of function of a sum of a variable tail current of the first differential amplifier and a variable tail current of the second differential amplifier.

Abstract: Quadrature clocking schemes are widely used in modern communications systems, but often suffer from phase imbalance. Conventional solutions that attempt to address this phase imbalance, however, are generally large and use a substantial amount of power. Here, however, a correction circuit is provided that can locally correct for phase imbalance without the need for bulky and high power consuming circuitry.

Abstract: Quadrature clocking schemes are widely used in modern communications systems, but often suffer from phase imbalance. Conventional solutions that attempt to address this phase imbalance, however, are generally large and use a substantial amount of power. Here, however, a correction circuit is provided that can locally correct for phase imbalance without the need for bulky and high power consuming circuitry.

Abstract: A method and apparatus for correcting the duty cycle of an uncorrected differential clock signal having a sinusoidal characteristic and outputting a corrected differential square wave clock signal. In the method, the uncorrected differential clock signal is provided as an uncorrected differential current to a pair of summing nodes. A correction differential voltage is generated as a signal corresponding to the inverse of the corrected differential clock signal and having a common mode voltage of one of the correction differential signals relative to a common mode voltage of the other of the correction differential voltages that depends on the duty cycle of the uncorrected differential clock signal. A correction differential current is generated, corresponding to the correction differential voltage.

Abstract: The duty cycle for a periodic signal such as a clock signal is idealized by feeding back duty cycle information. Duty cycle information is detected by a capacitor connected in serial with a resistor across the outputs of a feedback differential transistor pair. Over time, the capacitor will be charged or discharged when the duty cycle varies from fifty percent. The detected duty cycle information is fed back to an amplifier where the incoming clock signal is mixed with the feedback signal. The amplifier itself comprises a first differential comparator stage receiving the uncorrected clock signal, a gain stage that amplifies and level shifts the feedback signal, and a second differential pair receiving the amplified feedback signal.