Abstract: A neuron simulation circuit and a neural network apparatus. The neuron simulation circuit includes an operational amplifier, a first resistive device and a second resistive device. The operational amplifier includes a first input terminal, a second input terminal, and an output terminal. The first resistive device is connected between the first input terminal or the second input terminal of the operational amplifier and the output terminal of the operational amplifier. The second resistive device is connected between the output terminal of the operational amplifier and an output terminal of the neuron simulation circuit. The second resistive device includes a threshold switching memristor, and a first terminal of the threshold switching memristor is electrically connected with the output terminal of the neuron simulation circuit. At least one of the first resistive device and the second resistive device includes a dynamic memristor.

Abstract: A storage and computation integrated apparatus and a calibration method therefor. The storage and computation integrated apparatus includes a first processing unit, which includes: a first computation memristor array; a first calibration memristor array; and a first processing unit. The calibration method includes: determining, by means of off-chip training, a first computation weight matrix which corresponds to a first computation memristor array, and writing the first computation weight matrix into the first computation memristor array; and on the basis of the first computation memristor array where the first computation weight matrix has been written and the first computation weight matrix, performing on-chip training on a first calibration memristor array, so as to adjust a weight value of the first calibration memristor array.

Abstract: A data processing method based on a memristor array and an electronic apparatus are disclosed. The data processing method based on a memristor array includes: acquiring a plurality of first analog signals; setting the memristor array, and writing data corresponding to a convolution parameter matrix of a convolution processing into the memristor array; inputting the plurality of first analog signals respectively into a plurality of column signal input terminals of the memristor array that has been set, controlling operation of the memristor array to perform the convolution processing on the plurality of first analog signals, and obtaining a plurality of second analog signals after performing the convolution processing at a plurality of row signal output terminals of the memristor array, respectively.

Abstract: The disclosure relates to the technical filed of organic synthesis, in particular to a method for preparing veratrole. In the disclosure, veratrole is prepared by using lithium hydroxide instead of sodium hydroxide, catechol as raw material, and dimethyl sulfate as methylating agent. Comparing with the existing method of adding sodium hydroxide solution, the method according to the disclosure allows reduced reaction temperature, shortened reaction time, and thereby improves the stability and safety of the reaction and the product yield. The experimental data of the examples in the disclosure shows a veratrole yield up to 95%. Furthermore, the preparation method according to the disclosure does not need to be carried out under a reflux condition, the operation of which is simpler, thereby further improving the safety and stability of the reaction.

Abstract: A computing apparatus and a robustness processing method thereof. The robustness processing method includes: based on model parameters of a target algorithm model, obtaining a mapping relationship between the model parameters and the first computing memristor array; based on an influence factor that determines a critical weight device, determining a way to obtain a weight criticality of the plurality of memristor devices from the influence factor; obtaining an input set of the algorithm model, and determining a criticality value for each of the plurality of memristor devices according to the way; determining a critical weight device among the plurality of memristor devices according to the criticality value for each of the plurality of memristor devices; and based on the critical weight device, performing an optimization processing on the first processing unit.

Abstract: At least one embodiment of the present disclosure provides a data processing method based on a memristor array and an electronic apparatus. The data processing method includes: acquiring a plurality of first analog signals; setting the memristor array, and writing data of a parameter matrix corresponding to the data processing into the memristor array; and inputting the plurality of first analog signals into a plurality of column signal input terminals of the set memristor array, respectively, controlling operation of the memristor array to perform the data processing on the plurality of first analog signals, and obtaining a plurality of second analog signals after performing the data processing at a plurality of row signal output terminals of the memristor array, respectively.

Abstract: This application discloses a conductive paste, a preparation method thereof. The conductive paste comprises: a thermoplastic polyurethane, conductive particles, and an organic solvent, the thermoplastic polyurethane and the conductive particles being proportionally mixed in the organic solvent, and the thermoplastic polyurethane being dispersed in the form of particles among the conductive particles. A thermoplastic polyurethane elastomer is used as a binder, and the conductive particles are mixed in the organic solvent containing the thermoplastic polyurethane elastomer. The conductive particles ensure the conductivity of the conductive film prepared using the conductive paste. The thermoplastic polyurethane has strong adhesion ability, and is suitable for use on the surface of most substrates, to form a conductive film with good adhesion and no cracking.

Abstract: A signal processing apparatus and a signal processing method are provided. The signal processing apparatus includes a memristor array, an input circuit, a first switching circuit, a second switching circuit, an output circuit, and a control circuit. The memristor array includes memristor units and is connected to source lines, word lines and bit lines. The control circuit is configured to control the first switching circuit to select at least one source line to apply at least one first signal to the at least one source line respectively, control the second switching circuit to select and activate at least one word line to apply the at least one first signal to a memristor unit corresponding to the at least one word line, and control the output circuit to output a plurality of second signals based on conductivity values of memristors of the memristor array.

Abstract: A neural network and its information processing method, information processing system. The neural network includes N layers of neuron layers connected to each other one by one, except for a first layer of neuron layer, each of the neurons of the other neuron layers includes m dendritic units and one hippocampal unit; the dendritic unit includes a resistance value graded device, the hippocampal unit includes a resistance value mutation device, and the m dendritic units can be provided with different threshold voltage or current, respectively; and the neurons on the nth layer neuron layer are connected to the m dendritic units of the neurons on the n+1th layer neuron layer; wherein N is an integer larger than 3, m is an integer larger than 1, n is an integer larger than 1 and less than N.

Abstract: A data processing apparatus and a data processing method.

Abstract: This application discloses a conductive paste, a preparation method thereof, and a preparation method of a conductive film using the conductive paste. The conductive paste comprises: a thermoplastic polyurethane, conductive particles, and an organic solvent, the thermoplastic polyurethane and the conductive particles being proportionally mixed in the organic solvent, and the thermoplastic polyurethane being dispersed in the form of particles among the conductive particles. A thermoplastic polyurethane elastomer is used as a binder, and the conductive particles are mixed in the organic solvent containing the thermoplastic polyurethane elastomer. The conductive particles ensure the conductivity of the conductive film prepared using the conductive paste. The thermoplastic polyurethane has strong adhesion ability, and is suitable for use on the surface of most substrates, to form a conductive film with good adhesion and no cracking.

Abstract: A memristor and a preparation method thereof are provided. The memristor includes at least one memristive unit, each of the at least one memristive unit includes a transistor and at least one memristive component, the transistor includes a source electrode and a drain electrode; and each of the at least one memristive component includes a first electrode, a resistive layer, a second electrode, and a passivation layer, the first electrode is electrically connected with the source electrode or the drain electrode; the resistive layer is provided between the first electrode and the second electrode; and the passivation layer at least covers a sidewall of the resistive layer.

Abstract: A storage and computation integrated apparatus and a calibration method therefor. The storage and computation integrated apparatus includes a first processing unit, which includes: a first computation memristor array; a first calibration memristor array; and a first processing unit. The calibration method includes: determining, by means of off-chip training, a first computation weight matrix which corresponds to a first computation memristor array, and writing the first computation weight matrix into the first computation memristor array; and on the basis of the first computation memristor array where the first computation weight matrix has been written and the first computation weight matrix, performing on-chip training on a first calibration memristor array, so as to adjust a weight value of the first calibration memristor array.

Abstract: A storage device may be used in a neural network. The storage device includes a memristor unit, a current-controlled circuit, and a write circuit. The memristor unit has a structure of one-transistor and one-resistive random access memory (1T1R). The current-controlled circuit is configured to limit a current passing through the memristor unit to a target current, where the target current is determined based on target conductance of the memristor unit and a gate voltage of the transistor, and the target conductance is used to indicate target data to be written into the memristor unit. The write circuit is configured to load a write voltage to the memristor unit in cooperation with the current-controlled circuit, to write the target data to the memristor unit.

Abstract: Disclosed are a parallel acceleration method for a memristor-based neural network, a parallel acceleration processor based on a memristor-based neural network and a parallel acceleration device based on a memristor-based neural network. The neural network includes a plurality of functional layers sequentially provided, wherein the plurality of functional layers include a first functional layer and a second functional layer following the first functional layer, the first functional layer includes a plurality of first memristor arrays in parallel, and the plurality of first memristor arrays are configured to execute an operation of the first functional layer in parallel and to output a result of the operation to the second functional layer. The parallel acceleration method includes: executing the operation of the first functional layer in parallel via the plurality of first memristor arrays and outputting the result of the operation to the second functional layer.

Abstract: A data processing method based on a memristor array and an electronic apparatus are disclosed. The data processing method based on a memristor array includes: acquiring a plurality of first analog signals; setting the memristor array, and writing data corresponding to a convolution parameter matrix of a convolution processing into the memristor array; inputting the plurality of first analog signals respectively into a plurality of column signal input terminals of the memristor array that has been set, controlling operation of the memristor array to perform the convolution processing on the plurality of first analog signals, and obtaining a plurality of second analog signals after performing the convolution processing at a plurality of row signal output terminals of the memristor array, respectively.

Abstract: Disclosed are a quantization method and quantization apparatus for a weight of a neural network, and a storage medium. The neural network is implemented on the basis of a crossbar-enabled analog computing-in-memory (CACIM) system, and the quantization method includes: acquiring a distribution characteristic of a weight; and determining, according to the distribution characteristic of the weight, an initial quantization parameter for quantizing the weight to reduce a quantization error in quantizing the weight. The quantization method provided by the embodiments of the present disclosure does not pre-define the quantization method used, but determines the quantization parameter used for quantizing the weight according to the distribution characteristic of the weight to reduce the quantization error, so that the effect of the neural network model is better under the same mapping overhead, and the mapping overhead is smaller under the same effect of the neural network model.

Abstract: A compilation method, a compilation apparatus suitable for an In-Memory Computing apparatus, a computing device and a storage medium. The compilation method includes: acquiring calculation information of an algorithm to be compiled; converting the algorithm to be compiled into the first intermediate representation according to the calculation information; mapping the first intermediate representation to the second intermediate representation; and compiling the algorithm to be compiled into instruction information recognized by the In-Memory Computing apparatus according to the hardware information, to make the In-Memory Computing apparatus execute the instruction information. The compilation method may compile the calculation information into instructions that may be directly executed by the In-Memory Computing apparatus, so as to realize the effect of accelerating the operations of various algorithms by using the In-Memory Computing apparatus.

Abstract: A signal processing device and a signal processing method. The signal processing device includes a receiver, a memristor array and a classifier. The receiver is configured to receive a first signal. The memristor array includes a plurality of memristor units, each of the plurality of memristor units includes a memristor, and the memristor array is configured to apply the first signal that has been received to at least one memristor unit of the plurality of memristor units and output a second signal based on a memristor resistance value distribution of the memristor array. The classifier is configured to classify the second signal outputted from the memristor array to obtain a type of the first signal.

Abstract: At least one embodiment of the present disclosure provides a reservoir computing apparatus and a data processing method. The reservoir computing apparatus includes: a signal input circuit, configured to receive an input signal; a reservoir circuit, including a plurality of reservoir sub-circuits, in which each reservoir sub-circuit includes a mask sub-circuit and a rotating neuron sub-circuit, the mask sub-circuit is configured to perform a first processing on the input signal with a first weight to obtain a first processing result, and the rotating neuron sub-circuit is configured to perform a second processing on the first processing result to obtain a second processing result; and an output layer circuit, configured to multiply a plurality of second processing results by a second weight matrix to obtain a third processing result. The reservoir computing apparatus optimizes operation efficiency and reduces implementation costs.