Patents by Inventor Huaqiang Wu

Huaqiang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200237311
    Abstract: A signal processing device and a signal processing method. The signal processing device includes a receiver, a memristor array and a classifier. The receiver is configured to receive a first signal. The memristor array includes a plurality of memristor units, each of the plurality of memristor units includes a memristor, and the memristor array is configured to apply the first signal that has been received to at least one memristor unit of the plurality of memristor units and output a second signal based on a memristor resistance value distribution of the memristor array. The classifier is configured to classify the second signal outputted from the memristor array to obtain a type of the first signal.
    Type: Application
    Filed: January 23, 2020
    Publication date: July 30, 2020
    Applicant: Tsinghua University
    Inventors: Xinyi Li, Huaqiang Wu, He Qian, Bin Gao
  • Publication number: 20200175379
    Abstract: A generative adversarial network device and a training method thereof. The generative adversarial network device includes a generator and a discriminator. The generator is configured to generate a first sample according to an input data; the discriminator is coupled to the generator, and is configured to receive the first sample and be trained based on the first sample; the generator includes a first memristor array serving as a first weight array. The generative adversarial network device can omit a process of adding noise to fake samples generated by the generator, thereby saving training time, reducing resource consumption and improving training speed of the generative adversarial network.
    Type: Application
    Filed: December 1, 2019
    Publication date: June 4, 2020
    Applicant: Tsinghua University
    Inventors: Huaqiang Wu, Bin Gao, Yudeng Lin, He Qian
  • Patent number: 10668090
    Abstract: Disclosed are a liver specific delivery (LSD)-based antiviral prodrug nucleoside cyclophosphate compound and uses thereof, and in particular, provided are a compound of formula (I), and an isomer, a pharmaceutically acceptable salt, a hydrate and a solvate thereof, and the corresponding pharmaceutical composition. The present invention also provides uses of the present compounds, alone or in combination with other antiviral drugs, in the treatment of the diseases caused by hepatitis B virus (HBV), hepatitis D virus (HDV) and human immunodeficiency virus (HIV).
    Type: Grant
    Filed: December 22, 2018
    Date of Patent: June 2, 2020
    Assignee: ZHEJIANG PALO ALTO PHARMACEUTICALS, INC
    Inventors: Zhijian Xi, Huaqiang Xu, Chunping Lu, Zhongshan Wu, Feng Sun, Zhenwei Zhang
  • Publication number: 20200048299
    Abstract: Disclosed herein are a liver specific delivery (LSD)-based antiviral prodrug nucleoside cyclophosphate compound and uses thereof. Specifically, this application provides a compound of formula (I), or an isomer, a pharmaceutically acceptable salt, a hydrate, a solvate or a pharmaceutical composition thereof. This application also provides an application of the compound alone or in combination with other antiviral drugs in the treatment for viruses, particularly hepatitis C virus (HCV).
    Type: Application
    Filed: October 18, 2019
    Publication date: February 13, 2020
    Inventors: Zhijian XI, Huaqiang XU, Chunping LU, Zhongshan WU, Feng SUN
  • Patent number: 10475512
    Abstract: An operation method of a resistance random access memory and a resistance random access memory apparatus are provided. The method includes: applying an initial reset voltage to a storage unit; carrying out a read check operation to acquire a resistance value of the storage unit; judging whether the resistance value of the storage unit reaches a preset target resistance value in a high resistance state; if the resistance value of the storage unit is less than the preset target resistance value in the high resistance state, applying a set voltage to the storage unit to set the storage unit to a preset target resistance value in a low resistance state, then applying a reset voltage of which an amount is increased to the storage unit, and repeating the read check operation and the subsequent steps until the storage unit reaches the preset target resistance value in the high resistance state.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: November 12, 2019
    Assignee: Tsinghua University
    Inventors: Chen Wang, Huaqiang Wu, He Qian, Bin Gao
  • Patent number: 10468099
    Abstract: A circuit structure for implementing a physical unclonable function and a driving method thereof, an integrated circuit chip and an authentication method thereof, an electronic device are disclosed. The circuit structure includes: a multilayer circuit, a first address circuit and an output circuit, the multilayer circuit includes a first RRAM device array which is addressable and a second RRAM device array which is addressable; the first address circuit is configured to map a resistance value of a second RRAM device in the second RRAM device array to a first address; the first address is used for positioning a selected first RRAM device; and the output circuit is configured to acquire and process a resistance value of the selected first RRAM device and output a processing result.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: November 5, 2019
    Assignee: Tsinghua University
    Inventors: Huaqiang Wu, Yachuan Pang, Bin Gao, He Qian
  • Patent number: 10333455
    Abstract: A system and method for speed regulation of a VFD circuit via an anti-windup control scheme that provides consistent speed response with no overshoot is disclosed. A control system for operating the VFD circuit includes a feedback controller programmed to receive a speed of a motor operating responsive to an initial torque command and process the speed of the motor to generate a feedback controller output. A feedforward controller of the control system is programmed to process a speed reference to generate a feedforward controller output. A command module of the control system is programmed to determine a torque command based on the processed outputs of the feedback and feedforward controllers and operate the VFD circuit to control the motor according to the torque command.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: June 25, 2019
    Assignee: Eaton Intelligent Power Limited
    Inventors: Xiaomeng Cheng, Huaqiang Li, Peijun Zhu, Dongxiao Wu, Kayle Wang, Qian Zhang
  • Publication number: 20190088325
    Abstract: A circuit structure for implementing a physical unclonable function and a driving method thereof, an integrated circuit chip and an authentication method thereof, an electronic device are disclosed. The circuit structure includes: a multilayer circuit, a first address circuit and an output circuit, the multilayer circuit includes a first RRAM device array which is addressable and a second RRAM device array which is addressable; the first address circuit is configured to map a resistance value of a second RRAM device in the second RRAM device array to a first address; the first address is used for positioning a selected first RRAM device; and the output circuit is configured to acquire and process a resistance value of the selected first RRAM device and output a processing result.
    Type: Application
    Filed: September 17, 2018
    Publication date: March 21, 2019
    Inventors: Huaqiang Wu, Yachuan PANG, Bin Gao, He Qian
  • Publication number: 20190074435
    Abstract: A resistive random access memory and a manufacture method thereof are provided. The resistive random access memory includes: a first electrode, a second electrode, a resistive layer between the first electrode and the second electrode, and at least one thermal enhanced layer; the thermal enhanced layer is adjacent to the resistive layer, and a thermal conductivity of the thermal enhanced layer is less than a thermal conductivity of the first electrode and a thermal conductivity of the second electrode.
    Type: Application
    Filed: September 6, 2018
    Publication date: March 7, 2019
    Inventors: Huaqiang Wu, Wei Wu, Bin Gao, He Qian
  • Publication number: 20180330788
    Abstract: An operation method of a resistance random access memory and a resistance random access memory apparatus are provided. The method includes: applying an initial reset voltage to a storage unit; carrying out a read check operation to acquire a resistance value of the storage unit; judging whether the resistance value of the storage unit reaches a preset target resistance value in a high resistance state; if the resistance value of the storage unit is less than the preset target resistance value in the high resistance state, applying a set voltage to the storage unit to set the storage unit to a preset target resistance value in a low resistance state, then applying a reset voltage of which an amount is increased to the storage unit, and repeating the read check operation and the subsequent steps until the storage unit reaches the preset target resistance value in the high resistance state.
    Type: Application
    Filed: December 22, 2016
    Publication date: November 15, 2018
    Inventors: Chen Wang, Huaqiang Wu, He Qian, Bin Gao
  • Patent number: 9712124
    Abstract: The present disclosure provides a distributed amplifier, including: a drain transmission line; a gate transmission line; GFETs, in which sources of the graphene field-effect transistors are respectively grounded; gates of the graphene field-effect transistors respectively connected with a plurality of first shunt capacitors which are grounded; the gate transmission line is connected with a plurality of first nodes respectively between the gates of the graphene field-effect transistors and the plurality of first shunt capacitors, having a plurality of first inductors respectively between each two first nodes; drains of the graphene field-effect transistors respectively connected with a plurality of second shunt capacitors which are grounded; the drain transmission line is connected with a plurality of second nodes respectively between the drains of the graphene field-effect transistors and the plurality of second shunt capacitors, having a plurality of second inductors respectively between each two second node
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: July 18, 2017
    Assignee: Tsinghua University
    Inventors: Huaqiang Wu, Hongming Lyu, He Qian, Zhiping Yu, Yilin Huang, Jinyu Zhang
  • Patent number: 9659733
    Abstract: Method for preparing a molybdenum disulfide film used in a field emission device, including: providing a sulfur vapor; blowing the sulfur vapor into a reaction chamber having a substrate and MoO3 powder to generate a gaseous MoOx; feeding the sulfur vapor into the reaction chamber sequentially, heating the reaction chamber to a predetermined reaction temperature and maintaining for a predetermined reaction time, and then cooling the reaction chamber to a room temperature and maintaining for a second reaction time to form a molybdenum disulfide film on the surface of the substrate, in which the molybdenum disulfide film grows horizontally and then grows vertically. The method according to the present disclosure is simple and easy, and the field emission property of the MoS2 film obtained is good.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: May 23, 2017
    Assignee: Tsinghua University
    Inventors: Huaqiang Wu, Shuoguo Yuan, Han Li, He Qian
  • Patent number: 9455352
    Abstract: Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: September 27, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Ning Cheng, Huaqiang Wu, Hiro Kinoshita, Jihwan Choi, Angela Hui
  • Publication number: 20160254790
    Abstract: The present disclosure provides a distributed amplifier, including: a drain transmission line; a gate transmission line; GFETs, in which sources of the graphene field-effect transistors are respectively grounded; gates of the graphene field-effect transistors respectively connected with a plurality of first shunt capacitors which are grounded; the gate transmission line is connected with a plurality of first nodes respectively between the gates of the graphene field-effect transistors and the plurality of first shunt capacitors, having a plurality of first inductors respectively between each two first nodes; drains of the graphene field-effect transistors respectively connected with a plurality of second shunt capacitors which are grounded; the drain transmission line is connected with a plurality of second nodes respectively between the drains of the graphene field-effect transistors and the plurality of second shunt capacitors, having a plurality of second inductors respectively between each two second node
    Type: Application
    Filed: July 14, 2015
    Publication date: September 1, 2016
    Inventors: HONGMING LYU, ZHIPING YU, YILIN HUANG, JINYU ZHANG, HUAQIANG WU, HE QIAN
  • Publication number: 20160118586
    Abstract: A method for forming a stacked structure includes steps of: providing a first layer; oxidizing at least a part of the first layer to form a first oxide layer on the first layer; forming a second layer on the first oxide layer; and forming a second oxide layer between the first oxide layer and the second layer by rapid thermal annealing.
    Type: Application
    Filed: May 28, 2014
    Publication date: April 28, 2016
    Inventors: Huaqiang WU, Minghao WU, Yue BAI, He QIAN
  • Publication number: 20160108521
    Abstract: The present disclosure relates to a method for preparing a molybdenum disulfide film used in a field emission device, including: providing a sulfur vapor; blowing the sulfur vapor into a reaction chamber having a substrate and MoO3 powder to generate a gaseous MoOx; feeding the sulfur vapor into the reaction chamber sequentially, heating the reaction chamber to a predetermined reaction temperature and maintaining for a predetermined reaction time, and then cooling the reaction chamber to a room temperature and maintaining for a second reaction time to form a molybdenum disulfide film on the surface of the substrate, in which the molybdenum disulfide film grows horizontally and then grows vertically. The method according to the present disclosure is simple and easy, and the field emission property of the MoS2 film obtained is good.
    Type: Application
    Filed: June 16, 2015
    Publication date: April 21, 2016
    Inventors: Huaqiang WU, Shuoguo YUAN, Han LI, He QIAN
  • Publication number: 20160072062
    Abstract: An Al-W-O stack structure applicable to a resistive random access memory according to an embodiment of the invention comprises a tungsten top electrode, a tungsten oxide layer formed on the tungsten lower electrode, an aluminum oxide layer formed on the tungsten oxide layer and an aluminum top electrode formed on the aluminum oxide layer. The invention utilizes the different properties of two metals, namely aluminum and tungsten in bonding with oxygen ions, to obtain a resistive random access memory with more stable performances, lower power consumption and larger high resistance-low resistance ratio.
    Type: Application
    Filed: May 27, 2014
    Publication date: March 10, 2016
    Applicant: TSINGHUA UNIVERSITY
    Inventors: Huaqiang WU, Yue BAI, Minghao WU, He QIAN
  • Patent number: 9245895
    Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: January 26, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Ning Cheng, Kuo-Tung Chang, Hiro Kinoshita, Chih-Yuh Yang, Lei Xue, Chungho Lee, Minghao Shen, Angela Hui, Huaqiang Wu
  • Publication number: 20150325790
    Abstract: A method for forming a resistive random access memory is provided. The method comprises: steps of: S1) providing a silicon substrate; S2) forming an isolation layer on the silicon substrate; S3) forming a bottom electrode on the isolation layer; S4) forming a resistive switching material layer on the bottom electrode by magnetron sputtering at room temperature, comprising: S41) forming a first resistive switching layer of TaOx on the bottom electrode by magnetron sputtering under a first deposit pressure and in a first atmosphere, in which 0<x<2; and S42) forming a second resistive switching layer of TaOy on the first resistive switching layer by magnetron sputtering under a second deposit pressure and in a second atmosphere, in which 0<y<2.5; S5) forming a top electrode on the resistive switching material layer; and S6) removing the resistive switching materials TaOx and TaOy sputtered onto contacts of the bottom electrode in step S4.
    Type: Application
    Filed: December 25, 2013
    Publication date: November 12, 2015
    Inventors: HUAQIANG WU, XINYI LI, HE QIAN
  • Publication number: 20140167138
    Abstract: Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.
    Type: Application
    Filed: December 17, 2013
    Publication date: June 19, 2014
    Applicant: SPANSION LLC
    Inventors: Ning Cheng, Huaqiang Wu, Hiro Kinoshita, Jihwan Choi, Angela Hui