Abstract: A microelectrode, a method for manufacturing the microelectrode, a method for using the microelectrode, an occluding device, and a microelectrode system are provided. The microelectrode (10) includes a substrate (110) and a conductive layer (120) on the substrate (110), and the conductive layer (120) is configured to conduct an electrical signal. The substrate (110) is a flexible substrate and includes a cavity structure (111), and the cavity structure (111) is configured to contain or release a fluid. The hardness of the substrate (110) in the case where the cavity structure (111) contains the fluid is different from the hardness of the substrate (110) in the case where the cavity structure (111) does not contain the fluid. The microelectrode has good ductility and stable electrical performance, and the microelectrode is easy to be implanted into the biological tissue and not easy to result in the immune reaction of the biological tissue.

Abstract: A neuron simulation circuit and a neural network apparatus. The neuron simulation circuit includes an operational amplifier, a first resistive device and a second resistive device. The operational amplifier includes a first input terminal, a second input terminal, and an output terminal. The first resistive device is connected between the first input terminal or the second input terminal of the operational amplifier and the output terminal of the operational amplifier. The second resistive device is connected between the output terminal of the operational amplifier and an output terminal of the neuron simulation circuit. The second resistive device includes a threshold switching memristor, and a first terminal of the threshold switching memristor is electrically connected with the output terminal of the neuron simulation circuit. At least one of the first resistive device and the second resistive device includes a dynamic memristor.

Abstract: A resistive random access memory and a manufacture method thereof are provided. The resistive random access memory includes: a first electrode, a second electrode, a resistive layer between the first electrode and the second electrode, and at least one thermal enhanced layer; the thermal enhanced layer is adjacent to the resistive layer, and a thermal conductivity of the thermal enhanced layer is less than a thermal conductivity of the first electrode and a thermal conductivity of the second electrode.

Abstract: A compilation method, a compilation apparatus suitable for an In-Memory Computing apparatus, a computing device and a storage medium. The compilation method includes: acquiring calculation information of an algorithm to be compiled; converting the algorithm to be compiled into the first intermediate representation according to the calculation information; mapping the first intermediate representation to the second intermediate representation; and compiling the algorithm to be compiled into instruction information recognized by the In-Memory Computing apparatus according to the hardware information, to make the In-Memory Computing apparatus execute the instruction information. The compilation method may compile the calculation information into instructions that may be directly executed by the In-Memory Computing apparatus, so as to realize the effect of accelerating the operations of various algorithms by using the In-Memory Computing apparatus.

Abstract: A memristor and a preparation method thereof are provided. The memristor includes at least one memristive unit, each of the at least one memristive unit includes a transistor and at least one memristive component, the transistor includes a source electrode and a drain electrode; and each of the at least one memristive component includes a first electrode, a resistive layer, a second electrode, and a passivation layer, the first electrode is electrically connected with the source electrode or the drain electrode; the resistive layer is provided between the first electrode and the second electrode; and the passivation layer at least covers a sidewall of the resistive layer.

Abstract: This application provides a storage device and a data writing method. The storage device may be used in a neural network. The storage device includes a memristor unit, a current-controlled circuit, and a write circuit. The memristor unit has a structure of one-transistor and one-resistive random access memory 1T1R. The current-controlled circuit is configured to limit a current passing through the memristor unit to a target current, where the target current is determined based on target conductance of the memristor unit and a gate voltage of the transistor, and the target conductance is used to indicate target data to be written into the memristor unit. The write circuit is configured to load a write voltage to the memristor unit in cooperation with the current-controlled circuit, to write the target data to the memristor unit.

Abstract: A signal processing apparatus and a signal processing method are provided. The signal processing apparatus includes a memristor array, an input circuit, a first switching circuit, a second switching circuit, an output circuit, and a control circuit. The memristor array includes memristor units and is connected to source lines, word lines and bit lines. The control circuit is configured to control the first switching circuit to select at least one source line to apply at least one first signal to the at least one source line respectively, control the second switching circuit to select and activate at least one word line to apply the at least one first signal to a memristor unit corresponding to the at least one word line, and control the output circuit to output a plurality of second signals based on conductivity values of memristors of the memristor array.

Abstract: An information processing circuit and an information processing method. The information processing circuit includes: a signal acquisition circuit and a signal processing circuit, the signal acquisition circuit is configured to acquire a plurality of initial neural signals that are different, the signal processing circuit includes a plurality of memristors and is configured to process the plurality of initial neural signals through the plurality of memristors, and the plurality of memristors includes a plurality of first memristors, the plurality of first memristors are arranged in an array to obtain a preprocessing array, the preprocessing array is configured to extract features of the plurality of initial neural signals to obtain a plurality of feature information.

Abstract: Disclosed are a video stitching method and a video stitching device. The video stitching method is applicable for stitching a first video and a second video, and includes: performing feature extraction, feature matching and screening on a first target frame of the first video and a second target frame of the second video, so as to obtain a first feature point pair set; performing forward tracking on the first target frame and the second target frame, so as to obtain a second feature point pair set; performing backward tracking on the first target frame and the second target frame, so as to obtain a third feature point pair set; and calculating a geometric transformation relationship between the first target frame and the second target frame according to a union of the first feature point pair set, the second feature point pair set and the third feature point pair set.

Abstract: A nanowire transistor and a manufacture method thereof are provided. The nanowire transistor includes a semiconductor wire, a semiconductor layer, a source electrode and a drain electrode. The semiconductor wire includes a first semiconductor material and includes a source region, a drain region, and a channel region, along an axial direction of the semiconductor wire, the channel region is between the source region and the drain region; the semiconductor layer includes a second semiconductor material and covers the channel region of the semiconductor wire; the source electrode is in the source region of the semiconductor wire and is in direct contact with the source region of the semiconductor wire, and the drain electrode is in the drain region of the semiconductor wire and is in direct contact with the drain region of the semiconductor wire.

Abstract: A circuit structure and a driving method thereof, a neural network are disclosed. The circuit structure includes at least one circuit unit, each circuit unit includes a first group of resistive switching devices and a second group of resistive switching devices, the first group of resistive switching devices includes a resistance gradual-change device, the second group of resistive switching devices includes a resistance abrupt-change device, the first group of resistive switching devices and the second group of resistive switching devices are connected in series, in a case that no voltage is applied, a resistance value of the first group of resistive switching devices is larger than a resistance value of the second group of resistive switching devices. The circuit structure utilizes a resistance gradual-change device and a resistance abrupt-change device connected in series to form a neuron-like structure, so as to achieve to simulate functions of a human brain neuron.

Abstract: A neural network and its information processing method, information processing system. The neural network includes N layers of neuron layers connected to each other one by one, except for a first layer of neuron layer, each of the neurons of the other neuron layers includes m dendritic units and one hippocampal unit; the dendritic unit includes a resistance value graded device, the hippocampal unit includes a resistance value mutation device, and the m dendritic units can be provided with different threshold voltage or current, respectively; and the neurons on the nth layer neuron layer are connected to the m dendritic units of the neurons on the n+1th layer neuron layer; wherein N is an integer larger than 3, m is an integer larger than 1, n is an integer larger than 1 and less than N.

Abstract: A resistive random access memory and a manufacture method thereof are provided. The resistive random access memory includes: a first electrode, a second electrode, a resistive layer between the first electrode and the second electrode, and at least one thermal enhanced layer; the thermal enhanced layer is adjacent to the resistive layer, and a thermal conductivity of the thermal enhanced layer is less than a thermal conductivity of the first electrode and a thermal conductivity of the second electrode.

Abstract: A resistive random access memory and a manufacture method thereof are provided. The resistive random access memory includes: a first electrode, a second electrode, a resistive layer between the first electrode and the second electrode, and at least one thermal enhanced layer; the thermal enhanced layer is adjacent to the resistive layer, and a thermal conductivity of the thermal enhanced layer is less than a thermal conductivity of the first electrode and a thermal conductivity of the second electrode.

Abstract: A signal processing device and a signal processing method. The signal processing device includes a receiver, a memristor array and a classifier. The receiver is configured to receive a first signal. The memristor array includes a plurality of memristor units, each of the plurality of memristor units includes a memristor, and the memristor array is configured to apply the first signal that has been received to at least one memristor unit of the plurality of memristor units and output a second signal based on a memristor resistance value distribution of the memristor array. The classifier is configured to classify the second signal outputted from the memristor array to obtain a type of the first signal.

Abstract: A generative adversarial network device and a training method thereof. The generative adversarial network device includes a generator and a discriminator. The generator is configured to generate a first sample according to an input data; the discriminator is coupled to the generator, and is configured to receive the first sample and be trained based on the first sample; the generator includes a first memristor array serving as a first weight array. The generative adversarial network device can omit a process of adding noise to fake samples generated by the generator, thereby saving training time, reducing resource consumption and improving training speed of the generative adversarial network.

Abstract: An operation method of a resistance random access memory and a resistance random access memory apparatus are provided. The method includes: applying an initial reset voltage to a storage unit; carrying out a read check operation to acquire a resistance value of the storage unit; judging whether the resistance value of the storage unit reaches a preset target resistance value in a high resistance state; if the resistance value of the storage unit is less than the preset target resistance value in the high resistance state, applying a set voltage to the storage unit to set the storage unit to a preset target resistance value in a low resistance state, then applying a reset voltage of which an amount is increased to the storage unit, and repeating the read check operation and the subsequent steps until the storage unit reaches the preset target resistance value in the high resistance state.

Abstract: A circuit structure for implementing a physical unclonable function and a driving method thereof, an integrated circuit chip and an authentication method thereof, an electronic device are disclosed. The circuit structure includes: a multilayer circuit, a first address circuit and an output circuit, the multilayer circuit includes a first RRAM device array which is addressable and a second RRAM device array which is addressable; the first address circuit is configured to map a resistance value of a second RRAM device in the second RRAM device array to a first address; the first address is used for positioning a selected first RRAM device; and the output circuit is configured to acquire and process a resistance value of the selected first RRAM device and output a processing result.

Abstract: A circuit structure for implementing a physical unclonable function and a driving method thereof, an integrated circuit chip and an authentication method thereof, an electronic device are disclosed. The circuit structure includes: a multilayer circuit, a first address circuit and an output circuit, the multilayer circuit includes a first RRAM device array which is addressable and a second RRAM device array which is addressable; the first address circuit is configured to map a resistance value of a second RRAM device in the second RRAM device array to a first address; the first address is used for positioning a selected first RRAM device; and the output circuit is configured to acquire and process a resistance value of the selected first RRAM device and output a processing result.

Abstract: A resistive random access memory and a manufacture method thereof are provided. The resistive random access memory includes: a first electrode, a second electrode, a resistive layer between the first electrode and the second electrode, and at least one thermal enhanced layer; the thermal enhanced layer is adjacent to the resistive layer, and a thermal conductivity of the thermal enhanced layer is less than a thermal conductivity of the first electrode and a thermal conductivity of the second electrode.