Patents by Inventor Huaxiang Yin

Huaxiang Yin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230005937
    Abstract: The method for manufacturing a three-dimensional static random-access memory, including: manufacturing a first semiconductor structure including multiple MOS transistors and a first insulating layer thereon; bonding a first material layer to the first insulating layer to form a first substrate layer; manufacturing multiple first low-temperature MOS transistors at a low temperature on the first substrate layer, and forming a second insulating layer thereon to form a second semiconductor structure; bonding a second material layer to the second insulating layer to form a second substrate layer; manufacturing multiple second low-temperature MOS transistors at a low temperature on the second substrate layer, and forming a third insulating layer thereon to form a third semiconductor structure; and forming an interconnection layer which interconnets the first semiconductor structure, the second semiconductor structure and the third semiconductor structure.
    Type: Application
    Filed: December 10, 2019
    Publication date: January 5, 2023
    Inventors: Huaxiang Yin, Xiang Lin, Yanna Luo, Zhanfeng Liu
  • Patent number: 11476328
    Abstract: A stacked nanowire or nanosheet gate-all-around device, including: a silicon substrate; stacked nanowires or nanosheets located on the silicon substrate, extending along a first direction gate stacks and including multiple nanowires or nanosheets that are stacked; a gate stack, surrounding each of the stacked nanowires or nanosheets, and extending along a second direction, where first spacers are located on two sidewalls of the gate stack in the first direction; source-or-drain regions, located at two sides of the gate stack along the first direction; a channel region, including a portion of the stacked nanowires or nanosheets that is located between the first spacers. A notch structure recessed inward is located between the stacked nanowires or nanosheets and the silicon substrate, and includes an isolator that isolates the stacked nanowires or nanosheets from the silicon substrate. A method for manufacturing the stacked nanowire or nanosheet gate-all-around device is further provided.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: October 18, 2022
    Inventors: Yongliang Li, Xiaohong Cheng, Qingzhu Zhang, Huaxiang Yin, Wenwu Wang
  • Patent number: 11456218
    Abstract: A semiconductor device and a method for manufacturing the semiconductor device. Multiple stacks and an isolation structure among the multiple stacks are formed on a substrate. Each stack includes a first doping layer, a channel layer and a second doping layer. For each stack, the channel layer is laterally etched from at least one sidewall of said stack to form a cavity located between the first doping layer and the second doping layer, and a gate dielectric layer and a gate layer are formed in the cavity. A first sidewall of each stack is contact with the isolation structure, and the at least one sidewall does not include the first side wall. Costly high-precision etching is not necessary, and therefore a device with a small size and a high performance can be achieved with a simple process and a low cost. Diversified device structures can be provided on requirement.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: September 27, 2022
    Inventors: Guilei Wang, Henry H Radamson, Zhenzhen Kong, Junjie Li, Jinbiao Liu, Junfeng Li, Huaxiang Yin
  • Patent number: 11411091
    Abstract: A method for manufacturing a stacked gate-all-around nano-sheet CMOS device, including: providing a substrate with a fin structure, where a channel layer for an NMOS is a sacrificial layer for a PMOS, a channel layer for the PMOS is a sacrificial layer for the NMOS; and mobility of holes in the second material is greater than mobility of holes in the first material; forming a dummy gate stack extending across the fin structure; forming source-or-drain regions in the fin structure at two sides of the dummy gate stack; removing the dummy gate stack and the sacrificial layers covered by the dummy gate stack, to expose a surface of a part of the channel layer that is located between the source-or-drain regions, where a nano-sheet array is formed by the channel layer with the exposed surface; and forming a gate stack structure surrounding each nano sheet in the nano-sheet array.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: August 9, 2022
    Inventors: Huaxiang Yin, Tianchun Ye, Qingzhu Zhang, Jiaxin Yao
  • Publication number: 20220115513
    Abstract: A method for manufacturing a stacked gate-all-around nano-sheet CMOS device, including: providing a substrate with a fin structure, where a channel layer for an NMOS is a sacrificial layer for a PMOS, a channel layer for the PMOS is a sacrificial layer for the NMOS; and mobility of holes in the second material is greater than mobility of holes in the first material; forming a dummy gate stack extending across the fin structure; forming source-or-drain regions in the fin structure at two sides of the dummy gate stack; removing the dummy gate stack and the sacrificial layers covered by the dummy gate stack, to expose a surface of a part of the channel layer that is located between the source-or-drain regions, where a nano-sheet array is formed by the channel layer with the exposed surface; and forming a gate stack structure surrounding each nano sheet in the nano-sheet array.
    Type: Application
    Filed: October 30, 2019
    Publication date: April 14, 2022
    Inventors: Huaxiang YIN, Tianchun YE, Qingzhu ZHANG, Jiaxin YAO
  • Publication number: 20220085070
    Abstract: Provided are a three-dimensional vertical single transistor ferroelectric memory and a manufacturing method thereof. The ferroelectric memory comprises: a substrate; an insulating dielectric layer provided at the substrate; a channel structure extending through the insulating dielectric layer and connected to the substrate, the channel structure having a source/drain region and a channel region connected to the source/drain region; and a gate stack structure arranged around the channel structure and provided in the insulating dielectric layer opposite to the channel region, the gate stack structure comprising a ferroelectric insulation layer and a gate sequentially stacked in a direction away from the channel structure. The ferroelectric memory having the above structure can replace conventional DRAMs. Therefore, the invention realizes a high intensity high speed memory.
    Type: Application
    Filed: November 4, 2019
    Publication date: March 17, 2022
    Inventors: Huaxiang YIN, Zhaozhao HOU, Tianchun YE, Chaolei LI
  • Patent number: 11257933
    Abstract: A method for manufacturing a semiconductor device is provided. A first substrate and at least one second substrate are provided. A single crystal lamination structure is formed on the first substrate. The single crystal lamination structure includes at least one hetero-material layer and at least one channel material layer that are alternately laminated, each of the at least one hetero-material layer is bonded to an adjacent one of the at least one channel material layer at a side away from the first substrate, and each of the at least one channel material layer is formed from one of the at least one second substrate. At least one layer of nanowire or nanosheet is formed from the single crystal lamination structure. A gate dielectric layer and a gate which surround each of the at least one layer of nanowire or nanosheet is formed. A semiconductor device is also provided.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: February 22, 2022
    Assignee: Institute of Microelectronics, Chinese Academy
    Inventors: Huaxiang Yin, Qingzhu Zhang, Renren Xu
  • Publication number: 20210384080
    Abstract: A semiconductor device and a method for manufacturing the semiconductor device. Multiple stacks and an isolation structure among the multiple stacks are formed on a substrate. Each stack includes a first doping layer, a channel layer and a second doping layer. For each stack, the channel layer is laterally etched from at least one sidewall of said stack to form a cavity located between the first doping layer and the second doping layer, and a gate dielectric layer and a gate layer are formed in the cavity. A first sidewall of each stack is contact with the isolation structure, and the at least one sidewall does not include the first side wall. Costly high-precision etching is not necessary, and therefore a device with a small size and a high performance can be achieved with a simple process and a low cost. Diversified device structures can be provided on requirement.
    Type: Application
    Filed: August 27, 2020
    Publication date: December 9, 2021
    Inventors: Guilei WANG, Henry H. RADAMSON, Zhenzhen KONG, Junjie LI, Jinbiao LIU, Junfeng LI, Huaxiang YIN
  • Patent number: 11069808
    Abstract: A negative capacitance field effect transistor (NCFET) and a manufacturing method thereof. The NCFET includes: a substrate structure, including a MOS region; a gate insulating dielectric structure, covering the MOS region; and a metal gate stack layer, covering the gate insulating dielectric structure. The gate insulating dielectric structure includes an interface oxide layer, a HfO2 layer, a doping material layer, and a ferroelectric material layer, which are sequentially stacked along a direction away from the substrate structure. A ferroelectric material in the ferroelectric material layer is HfxA1-xO2, A represents a doping element, and 0.1?x?0.9. A material forming the doping material layer is AyOz or A, and a ratio of y/z is equal to 1/2, 2/3, 2/5 or 1/1. Ferroelectric characteristics, material stability, and material reliability of the NCFET are improved by increasing domain polarity of the ferroelectric material.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: July 20, 2021
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huaxiang Yin, Qingzhu Zhang, Zhaohao Zhang, Tianchun Ye
  • Publication number: 20210193822
    Abstract: A method for manufacturing a semiconductor device is provided. A first substrate and at least one second substrate are provided. A single crystal lamination structure is fonned on the first substrate. The single crystal lamination structure includes at least one hetero-material layer and at least one channel material layer that are alternately laminated, each of the at least one hetero-material layer is bonded to an adjacent one of the at least one channel material layer at a side away from the first substrate, and each of the at least one channel material layer is formed from one of the at least one second substrate. At least one layer of nanowire or nanosheet is formed from the single crystal lamination structure. A gate dielectric layer and a gate which surround each of the at least one layer of nanowire or nanosheet is formed. A semiconductor device is also provided.
    Type: Application
    Filed: September 23, 2020
    Publication date: June 24, 2021
    Inventors: Huaxiang YIN, Qingzhu ZHANG, Renren XU
  • Patent number: 11024708
    Abstract: A semiconductor device, including: a silicon substrate; multiple fin structures, formed on the silicon substrate, where each extends along a first direction; a shallow trench insulator, located among the multiple fin structures; a gate stack, intersecting with the multiple fin structures and extending along a second direction, where first spacers are formed on two sidewalls in the first direction of the gate stack; source-or-drain regions, formed on the multiple fin structures, and located at two sides of the gate stack along the first direction; and a channel region, including a portion of the multiple fin structures located between the first spacers. and notch structures. A notch structure recessed inward is located between each of the multiple fin structures and the silicon substrate. The notch structure includes an isolator that isolates each of the multiple fin structures from the silicon substrate.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: June 1, 2021
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Yongliang Li, Xiaohong Cheng, Qingzhu Zhang, Huaxiang Yin, Wenwu Wang
  • Publication number: 20210151557
    Abstract: A semiconductor device, including: a silicon substrate; multiple fin structures, formed on the silicon substrate, where each extends along a first direction; a shallow trench insulator, located among the multiple fin structures; a gate stack, intersecting with the multiple fin structures and extending along a second direction, where first spacers are formed on two sidewalls in the first direction of the gate stack; source-or-drain regions, formed on the multiple fin structures, and located at two sides of the gate stack along the first direction; and a channel region, including a portion of the multiple fin structures located between the first spacers. and notch structures. A notch structure recessed inward is located between each of the multiple fin structures and the silicon substrate. The notch structure includes an isolator that isolates each of the multiple fin structures from the silicon substrate.
    Type: Application
    Filed: March 20, 2020
    Publication date: May 20, 2021
    Inventors: Yongliang LI, Xiaohong CHENG, Qingzhu ZHANG, Huaxiang YIN, Wenwu WANG
  • Publication number: 20210151561
    Abstract: A stacked nanowire or nanosheet gate-all-around device, including: a silicon substrate; stacked nanowires or nanosheets located on the silicon substrate, extending along a first direction gate stacks and including multiple nanowires or nanosheets that are stacked; a gate stack, surrounding each of the stacked nanowires or nanosheets, and extending along a second direction, where first spacers are located on two sidewalls of the gate stack in the first direction; source-or-drain regions, located at two sides of the gate stack along the first direction; a channel region, including a portion of the stacked nanowires or nanosheets that is located between the first spacers. A notch structure recessed inward is located between the stacked nanowires or nanosheets and the silicon substrate, and includes an isolator that isolates the stacked nanowires or nanosheets from the silicon substrate. A method for manufacturing the stacked nanowire or nanosheet gate-all-around device is further provided.
    Type: Application
    Filed: March 20, 2020
    Publication date: May 20, 2021
    Inventors: Yongliang LI, Xiaohong CHENG, Qingzhu ZHANG, Huaxiang YIN, Wenwu WANG
  • Publication number: 20200335596
    Abstract: A gate-all-around nanowire device and a method for forming the gate-all-around nanowire device. A first fin and a dielectric layer on the first fin are formed on a substrate. The first fin includes the at least one first epitaxial layer and the at least one second epitaxial layer that are alternately stacked. The dielectric layer exposes a channel region of the first fin. A doping concentration at a lateral surface of the channel region and a doping concentration at a central region of the channel region are different from each other in the at least one second epitaxial layer. After the at least one first epitaxial layer is removed from the channel region, the at least one second epitaxial layer in the channel region serves as at least one nanowire. A gate surrounding the at least one nanowire is formed.
    Type: Application
    Filed: September 5, 2019
    Publication date: October 22, 2020
    Inventors: Huaxiang YIN, Jiaxin YAO, Qingzhu ZHANG, Zhaohao ZHANG, Tianchun YE
  • Publication number: 20200328309
    Abstract: A negative capacitance field effect transistor (NCFET) and a manufacturing method thereof. The NCFET includes: a substrate structure, including a MOS region; a gate insulating dielectric structure, covering the MOS region; and a metal gate stack layer, covering the gate insulating dielectric structure. The gate insulating dielectric structure includes an interface oxide layer, a HfO2 layer, a doping material layer, and a ferroelectric material layer, which are sequentially stacked along a direction away from the substrate structure. A ferroelectric material in the ferroelectric material layer is HfxA1-xO2, A represents a doping element, and 0.1?x?0.9. A material forming the doping material layer is AyOz or A, and a ratio of y/z is equal to 1/2, 2/3, 2/5 or 1/1. Ferroelectric characteristics, material stability, and material reliability of the NCFET are improved by increasing domain polarity of the ferroelectric material.
    Type: Application
    Filed: December 19, 2019
    Publication date: October 15, 2020
    Inventors: Huaxiang YIN, Qingzhu ZHANG, Zhaohao ZHANG, Tianchun YE
  • Patent number: 10708193
    Abstract: A device may comprise security processing units (SPUs) including a SPU to receive a session request. The SPU may identify global counter information and update counter information. The global counter information may include a global counter identifier and a global counter value. The update counter information may include an update counter identifier and an update counter value. The SPU may identify a global limit associated with the global counter, may determine that the global limit has not been met, and may cause the session to be created. The SPU may create a modified global counter value. The SPU may create a modified update counter value. The SPU may determine that a local update message is required based on the modified update counter value, and may provide the local update message to another SPU. The local update message may include the global counter identifier and the modified global counter value.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: July 7, 2020
    Assignee: Juniper Networks, Inc.
    Inventors: Xiao Ping Zhu, Huaxiang Yin, Zheling Yang, Chao Chen
  • Publication number: 20200211910
    Abstract: A multilayer MOS device and a method for manufacturing the same. The manufacturing method includes: providing a MOS device including n layers, where n is a natural number greater than zero; forming a semiconductor layer on the MOS device including n layers; forming a gate oxide layer and a dummy gate on the semiconductor layer sequentially, where at least a part of the gate oxide layer is located between the dummy gate and the semiconductor layer; forming a metal silicide layer in the semiconductor layer at two sides of the dummy gate, to obtain a MOS device of an (n+1)-th layer, where the metal silicide layer serves as a metallized source-drain region or the metal silicide layer is doped to form a metalized source-drain region; and connecting a MOS device of an n-th layer of the n layers with the MOS device of the (n+1)-th layer via metallic interconnection.
    Type: Application
    Filed: December 20, 2019
    Publication date: July 2, 2020
    Inventors: Huaxiang YIN, Qingzhu ZHANG, Xiang LIN
  • Patent number: 10390290
    Abstract: A first processing device may receive, from a first network device, a tunneling protocol message associated with a tunnel to be established between the first network device and a second network device. The first processing device may determine, based on the tunneling protocol message, a device identifier of the second network device. The first processing device may determine that a second processing device is to process a flow associated with the first network device and the second network device based on the device identifier of the second network device. The first processing device may provide information that identifies that the second processing device is to process the flow to permit the second processing device to process the flow associated with the first network device and the second network device.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: August 20, 2019
    Assignee: Juniper Networks, Inc.
    Inventors: Jing Zhang, Zengqiang Yuan, Mingming Quan, BinFang Sun, Lei Liang, Gaofeng Tian, Huaxiang Yin
  • Patent number: 10171436
    Abstract: A device includes a security process unit (SPU) associated with a logical ring of SPUs. The SPU receives a packet with an address associated with a malicious source, and creates, based on the packet, an entry in a data structure associated with the SPU. The entry includes information associated with the packet. The SPU provides an install message to a next SPU in the logical ring. The install message instructs the next SPU to create the entry in another data structure, and forward the install message to another SPU. The SPU receives the install message from a last SPU, and sets a state of the entry to active in the data structure based on receiving the install message from the last SPU. The SPU performs a particular action on another packet, associated with the malicious source, based on the setting the state of the entry to active.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: January 1, 2019
    Assignee: Juniper Networks, Inc.
    Inventors: Chao Chen, Xiao Ping Zhu, Huaxiang Yin, Zheling Yang
  • Publication number: 20180331934
    Abstract: A device may comprise security processing units (SPUs) including a SPU to receive a session request. The SPU may identify global counter information and update counter information. The global counter information may include a global counter identifier and a global counter value. The update counter information may include an update counter identifier and an update counter value. The SPU may identify a global limit associated with the global counter, may determine that the global limit has not been met, and may cause the session to be created. The SPU may create a modified global counter value. The SPU may create a modified update counter value. The SPU may determine that a local update message is required based on the modified update counter value, and may provide the local update message to another SPU. The local update message may include the global counter identifier and the modified global counter value.
    Type: Application
    Filed: July 20, 2018
    Publication date: November 15, 2018
    Inventors: Xiao Ping ZHU, Huaxiang YIN, Zheling YANG, Chao CHEN