Patents by Inventor Huaxiang Yin

Huaxiang Yin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250221031
    Abstract: A semiconductor structure and a method for manufacturing the same. The method comprises: providing a substrate comprising a first surface and a second surface opposite to each other; forming, on the first surface, a first transistor structure comprising a first channel layer, a first gate structure disposed on the first channel layer, and a first source-drain epitaxial layer disposed on two lateral sides of the first gate structure; providing, on the second surface, a second transistor structure comprising a second channel layer, a second gate structure disposed on the second channel layer, and a second source-drain epitaxial layer disposed on two lateral sides of the second gate structure; forming, in the second source-drain epitaxial layer and the substrate, a first conductive plug electrically connected to the first source-drain epitaxial layer; and forming a first interconnection layer on the first conductive plug and the second gate structure.
    Type: Application
    Filed: July 9, 2024
    Publication date: July 3, 2025
    Inventors: Huaxiang Yin, Yadong Zhang, Qingzhu Zhang, Feixiong Wang, Yunjiao Bao
  • Publication number: 20250212443
    Abstract: The present disclosure relates to a method of manufacturing a fin in a transistor and a method of manufacturing a fin field effect transistor. The method of manufacturing the fin in the transistor includes: epitaxially growing a semiconductor layer on a substrate; etching the semiconductor layer into a fin-shaped portion by using a spacer transfer technique; oxidizing a sidewall of the fin-shaped portion with ozone, so as to form an oxide film on the sidewall; and etching the oxide film by using an atomic layer etching method, so as to remove the oxide film.
    Type: Application
    Filed: October 3, 2024
    Publication date: June 26, 2025
    Inventors: Junfeng LI, Peng WANG, Guanqiao SANG, Lei CAO, Renjie JIANG, Qingkun LI, Qingzhu ZHANG, Huaxiang YIN, Jun LUO, Yihong LU, Wenjuan XIONG
  • Publication number: 20250212460
    Abstract: The present disclosure relates to a nanosheet gate-all-around transistor and a method of manufacturing a nanosheet gate-all-around transistor. The nanosheet gate-all-around transistor includes: a substrate having a shallow trench isolation structure on a surface of the substrate; a nanosheet stacking portion provided above the substrate, where the nanosheet stacking portion includes a stack formed by a plurality of nanosheets, the stack formed by the nanosheets constitutes a plurality of conductive channels, and the nanosheets are graphene nanosheets; a gate-all-around surrounding the nanosheet stacking portion; and a source/drain region located on two opposite sides of the nanosheet stacking portion, where a spacer is provided between the source/drain region and the gate-all-around.
    Type: Application
    Filed: September 24, 2024
    Publication date: June 26, 2025
    Inventors: Junfeng LI, Peng WANG, Guanqiao SANG, Renjie JIANG, Hang ZHANG, Qingzhu ZHANG, Huaxiang YIN, Jun LUO
  • Publication number: 20250133785
    Abstract: The present disclosure provides a stacked nanosheet gate-all-around device with an air spacer and a manufacturing method. The device includes: a substrate, where a first dielectric layer is on the substrate, a gap array is in the first dielectric layer, the gap array includes multiple gap units, and each gap unit is in a fin shape above the substrate; a nanosheet stacking portion above the gap unit, including a stack formed by multiple nanosheets, and the stack formed by the nanosheets constitutes multiple conductive channels; a gate-all-around surrounding the nanosheet stacking portion; and a source/drain region on two opposite sides of the nanosheet stacking portion, where an empty spacer is between the source/drain region and the gate-all-around. An interior of the gap array and an interior of the empty spacer are filled with at least one of air, a reducing gas, or an inert gas.
    Type: Application
    Filed: October 4, 2024
    Publication date: April 24, 2025
    Inventors: Qingzhu ZHANG, Lianlian LI, Anyan DU, Huaxiang YIN, Lei CAO, Jiaxin YAO, Zhaohao ZHANG, Qingkun LI, Guanqiao SANG
  • Publication number: 20250133773
    Abstract: The present disclosure relates to a stacked nanosheet gate-all-around device with an air spacer and a method of manufacturing a stacked nanosheet gate-all-around device with an air spacer. The stacked nanosheet gate-all-around device with the air spacer includes: a substrate with a shallow trench isolation structure on a surface of the substrate; a nanosheet stacking portion provided above the substrate, where the nanosheet stacking portion includes a stack formed by a plurality of nanosheets, and the stack formed by the nanosheets constitutes a plurality of conductive channels; a gate-all-around surrounding the nanosheet stacking portion; and a source/drain region located on two opposite sides of the nanosheet stacking portion, where an empty spacer is provided between the source/drain region and the gate-all-around, where an interior of the empty spacer is filled with at least one of air, a reducing gas, or an inert gas.
    Type: Application
    Filed: October 15, 2024
    Publication date: April 24, 2025
    Inventors: Qingzhu ZHANG, Lianlian LI, Anyan DU, Huaxiang YIN, Lei CAO, Jiaxin YAO, Zhaohao ZHANG, Qingkun LI, Guanqiao SANG
  • Publication number: 20250069653
    Abstract: The computing-in-memory circuit includes: an SRAM memory cell array including at least one memory cell connected between a first bit line and a second bit line, the memory cell includes a first inverter and a second inverter cross-coupled with each other, and the first inverter and the second inverter have an asymmetric configuration with respect to each other; a control circuit configured to: receive a first input signal, a second input signal and an operation mode control signal, process the first input signal and the second input signal according to operation mode control signal, so as to obtain a processed first input signal and a processed second input signal, and apply the processed first input signal and the processed second input signal to the first bit line and the second bit line, respectively; and a readout circuit configured to read out data stored in memory cell from the memory cell.
    Type: Application
    Filed: November 14, 2024
    Publication date: February 27, 2025
    Inventors: Huaxiang YIN, Xuexiang ZHANG, Jiaxin YAO
  • Publication number: 20250031417
    Abstract: A semiconductor device and a method for manufacturing the same. The method comprise: forming a first field-effect transistor (FET) disposed on a substrate and a first isolation layer disposed on the first FET; forming a first through hole in the first isolation layer, where a metal layer is deposited in the first through hole and is electrically connected to the first FET; forming a second isolation layer, which is disposed on the first isolation layer and the metal layer; and forming a second FET which is disposed on the second isolation layer, where a second through hole is disposed in the second FET and the second isolation layer, a metal material filled in the second through hole serves as a first contact plug, and the first contact plug is electrically connected to the metal layer. The metal layer serves as a power distribution network for both FETs.
    Type: Application
    Filed: December 18, 2023
    Publication date: January 23, 2025
    Inventors: Huaxiang YIN, Qingzhu ZHANG, Yadong ZHANG, Jiaxin YAO
  • Publication number: 20240379794
    Abstract: Provided are a three-dimensional stack field-effect transistor (3DS FET) and a method of manufacturing the same. According to embodiments, the 3DS FET includes: a lower active region arranged on a substrate, an upper active region above the lower active region and a gate stack. The lower active region includes: a fin extending in a first direction on the substrate, and lower source/drain portions at two opposite ends of the fin in the first direction, respectively. The upper active region includes: one or more nanosheets, a lowest nanosheet is spaced apart from the fin in a vertical direction relative to the substrate, and upper source/drain portions at two opposite ends of the one or more nanosheets in the first direction, respectively. The gate stack extends in a second direction intersecting with the first direction so as to intersect with the fin and the one or more nanosheets.
    Type: Application
    Filed: September 7, 2023
    Publication date: November 14, 2024
    Inventors: Huaxiang YIN, Peng ZHAO, Zhenhua WU, Jiaxin YAO
  • Patent number: 11839085
    Abstract: Provided are a three-dimensional vertical single transistor ferroelectric memory and a manufacturing method thereof. The ferroelectric memory comprises: a substrate; an insulating dielectric layer provided at the substrate; a channel structure extending through the insulating dielectric layer and connected to the substrate, the channel structure having a source/drain region and a channel region connected to the source/drain region; and a gate stack structure arranged around the channel structure and provided in the insulating dielectric layer opposite to the channel region, the gate stack structure comprising a ferroelectric insulation layer and a gate sequentially stacked in a direction away from the channel structure. The ferroelectric memory having the above structure can replace conventional DRAMs. Therefore, the invention realizes a high intensity high speed memory.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: December 5, 2023
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huaxiang Yin, Zhaozhao Hou, Tianchun Ye, Chaolei Li
  • Publication number: 20230326965
    Abstract: A semiconductor device and a method for manufacturing the same. The semiconductor device includes: a first gate-all-around (GAA) transistor disposed in the first region, including a first nanowire or nanosheet of at least one first layer, the at least one first layer and the substrate form a first group, among which all pairs of adjacent layers are separated by first distances, respectively; and a second GAA transistor disposed in the second region, including a second nanowire or nanosheet of at least two second layers, the at least two second layers and the substrate form a second group, among which the second layers are separated by second distances, respectively; where a minimum first distance is greater than a maximum second distance, and a quantity of the at least one first layer is less than a quantity of the at least two second layers.
    Type: Application
    Filed: December 22, 2022
    Publication date: October 12, 2023
    Inventors: Yongliang Li, Anlan Chen, Fei Zhao, Xiaohong Cheng, Huaxiang Yin, Jun Luo, Wenwu Wang
  • Patent number: 11594608
    Abstract: A gate-all-around nanowire device and a method for forming the gate-all-around nanowire device. A first fin and a dielectric layer on the first fin are formed on a substrate. The first fin includes the at least one first epitaxial layer and the at least one second epitaxial layer that are alternately stacked. The dielectric layer exposes a channel region of the first fin. A doping concentration at a lateral surface of the channel region and a doping concentration at a central region of the channel region are different from each other in the at least one second epitaxial layer. After the at least one first epitaxial layer is removed from the channel region, the at least one second epitaxial layer in the channel region serves as at least one nanowire. A gate surrounding the at least one nanowire is formed.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: February 28, 2023
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huaxiang Yin, Jiaxin Yao, Qingzhu Zhang, Zhaohao Zhang, Tianchun Ye
  • Publication number: 20230005937
    Abstract: The method for manufacturing a three-dimensional static random-access memory, including: manufacturing a first semiconductor structure including multiple MOS transistors and a first insulating layer thereon; bonding a first material layer to the first insulating layer to form a first substrate layer; manufacturing multiple first low-temperature MOS transistors at a low temperature on the first substrate layer, and forming a second insulating layer thereon to form a second semiconductor structure; bonding a second material layer to the second insulating layer to form a second substrate layer; manufacturing multiple second low-temperature MOS transistors at a low temperature on the second substrate layer, and forming a third insulating layer thereon to form a third semiconductor structure; and forming an interconnection layer which interconnets the first semiconductor structure, the second semiconductor structure and the third semiconductor structure.
    Type: Application
    Filed: December 10, 2019
    Publication date: January 5, 2023
    Inventors: Huaxiang Yin, Xiang Lin, Yanna Luo, Zhanfeng Liu
  • Patent number: 11476328
    Abstract: A stacked nanowire or nanosheet gate-all-around device, including: a silicon substrate; stacked nanowires or nanosheets located on the silicon substrate, extending along a first direction gate stacks and including multiple nanowires or nanosheets that are stacked; a gate stack, surrounding each of the stacked nanowires or nanosheets, and extending along a second direction, where first spacers are located on two sidewalls of the gate stack in the first direction; source-or-drain regions, located at two sides of the gate stack along the first direction; a channel region, including a portion of the stacked nanowires or nanosheets that is located between the first spacers. A notch structure recessed inward is located between the stacked nanowires or nanosheets and the silicon substrate, and includes an isolator that isolates the stacked nanowires or nanosheets from the silicon substrate. A method for manufacturing the stacked nanowire or nanosheet gate-all-around device is further provided.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: October 18, 2022
    Inventors: Yongliang Li, Xiaohong Cheng, Qingzhu Zhang, Huaxiang Yin, Wenwu Wang
  • Patent number: 11456218
    Abstract: A semiconductor device and a method for manufacturing the semiconductor device. Multiple stacks and an isolation structure among the multiple stacks are formed on a substrate. Each stack includes a first doping layer, a channel layer and a second doping layer. For each stack, the channel layer is laterally etched from at least one sidewall of said stack to form a cavity located between the first doping layer and the second doping layer, and a gate dielectric layer and a gate layer are formed in the cavity. A first sidewall of each stack is contact with the isolation structure, and the at least one sidewall does not include the first side wall. Costly high-precision etching is not necessary, and therefore a device with a small size and a high performance can be achieved with a simple process and a low cost. Diversified device structures can be provided on requirement.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: September 27, 2022
    Inventors: Guilei Wang, Henry H Radamson, Zhenzhen Kong, Junjie Li, Jinbiao Liu, Junfeng Li, Huaxiang Yin
  • Patent number: 11411091
    Abstract: A method for manufacturing a stacked gate-all-around nano-sheet CMOS device, including: providing a substrate with a fin structure, where a channel layer for an NMOS is a sacrificial layer for a PMOS, a channel layer for the PMOS is a sacrificial layer for the NMOS; and mobility of holes in the second material is greater than mobility of holes in the first material; forming a dummy gate stack extending across the fin structure; forming source-or-drain regions in the fin structure at two sides of the dummy gate stack; removing the dummy gate stack and the sacrificial layers covered by the dummy gate stack, to expose a surface of a part of the channel layer that is located between the source-or-drain regions, where a nano-sheet array is formed by the channel layer with the exposed surface; and forming a gate stack structure surrounding each nano sheet in the nano-sheet array.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: August 9, 2022
    Inventors: Huaxiang Yin, Tianchun Ye, Qingzhu Zhang, Jiaxin Yao
  • Publication number: 20220115513
    Abstract: A method for manufacturing a stacked gate-all-around nano-sheet CMOS device, including: providing a substrate with a fin structure, where a channel layer for an NMOS is a sacrificial layer for a PMOS, a channel layer for the PMOS is a sacrificial layer for the NMOS; and mobility of holes in the second material is greater than mobility of holes in the first material; forming a dummy gate stack extending across the fin structure; forming source-or-drain regions in the fin structure at two sides of the dummy gate stack; removing the dummy gate stack and the sacrificial layers covered by the dummy gate stack, to expose a surface of a part of the channel layer that is located between the source-or-drain regions, where a nano-sheet array is formed by the channel layer with the exposed surface; and forming a gate stack structure surrounding each nano sheet in the nano-sheet array.
    Type: Application
    Filed: October 30, 2019
    Publication date: April 14, 2022
    Inventors: Huaxiang YIN, Tianchun YE, Qingzhu ZHANG, Jiaxin YAO
  • Publication number: 20220085070
    Abstract: Provided are a three-dimensional vertical single transistor ferroelectric memory and a manufacturing method thereof. The ferroelectric memory comprises: a substrate; an insulating dielectric layer provided at the substrate; a channel structure extending through the insulating dielectric layer and connected to the substrate, the channel structure having a source/drain region and a channel region connected to the source/drain region; and a gate stack structure arranged around the channel structure and provided in the insulating dielectric layer opposite to the channel region, the gate stack structure comprising a ferroelectric insulation layer and a gate sequentially stacked in a direction away from the channel structure. The ferroelectric memory having the above structure can replace conventional DRAMs. Therefore, the invention realizes a high intensity high speed memory.
    Type: Application
    Filed: November 4, 2019
    Publication date: March 17, 2022
    Inventors: Huaxiang YIN, Zhaozhao HOU, Tianchun YE, Chaolei LI
  • Patent number: 11257933
    Abstract: A method for manufacturing a semiconductor device is provided. A first substrate and at least one second substrate are provided. A single crystal lamination structure is formed on the first substrate. The single crystal lamination structure includes at least one hetero-material layer and at least one channel material layer that are alternately laminated, each of the at least one hetero-material layer is bonded to an adjacent one of the at least one channel material layer at a side away from the first substrate, and each of the at least one channel material layer is formed from one of the at least one second substrate. At least one layer of nanowire or nanosheet is formed from the single crystal lamination structure. A gate dielectric layer and a gate which surround each of the at least one layer of nanowire or nanosheet is formed. A semiconductor device is also provided.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: February 22, 2022
    Assignee: Institute of Microelectronics, Chinese Academy
    Inventors: Huaxiang Yin, Qingzhu Zhang, Renren Xu
  • Publication number: 20210384080
    Abstract: A semiconductor device and a method for manufacturing the semiconductor device. Multiple stacks and an isolation structure among the multiple stacks are formed on a substrate. Each stack includes a first doping layer, a channel layer and a second doping layer. For each stack, the channel layer is laterally etched from at least one sidewall of said stack to form a cavity located between the first doping layer and the second doping layer, and a gate dielectric layer and a gate layer are formed in the cavity. A first sidewall of each stack is contact with the isolation structure, and the at least one sidewall does not include the first side wall. Costly high-precision etching is not necessary, and therefore a device with a small size and a high performance can be achieved with a simple process and a low cost. Diversified device structures can be provided on requirement.
    Type: Application
    Filed: August 27, 2020
    Publication date: December 9, 2021
    Inventors: Guilei WANG, Henry H. RADAMSON, Zhenzhen KONG, Junjie LI, Jinbiao LIU, Junfeng LI, Huaxiang YIN
  • Patent number: 11069808
    Abstract: A negative capacitance field effect transistor (NCFET) and a manufacturing method thereof. The NCFET includes: a substrate structure, including a MOS region; a gate insulating dielectric structure, covering the MOS region; and a metal gate stack layer, covering the gate insulating dielectric structure. The gate insulating dielectric structure includes an interface oxide layer, a HfO2 layer, a doping material layer, and a ferroelectric material layer, which are sequentially stacked along a direction away from the substrate structure. A ferroelectric material in the ferroelectric material layer is HfxA1-xO2, A represents a doping element, and 0.1?x?0.9. A material forming the doping material layer is AyOz or A, and a ratio of y/z is equal to 1/2, 2/3, 2/5 or 1/1. Ferroelectric characteristics, material stability, and material reliability of the NCFET are improved by increasing domain polarity of the ferroelectric material.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: July 20, 2021
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huaxiang Yin, Qingzhu Zhang, Zhaohao Zhang, Tianchun Ye