Abstract: A first processing device may receive, from a first network device, a tunneling protocol message associated with a tunnel to be established between the first network device and a second network device. The first processing device may determine, based on the tunneling protocol message, a device identifier of the second network device. The first processing device may determine that a second processing device is to process a flow associated with the first network device and the second network device based on the device identifier of the second network device. The first processing device may provide information that identifies that the second processing device is to process the flow to permit the second processing device to process the flow associated with the first network device and the second network device.

Abstract: A device includes a security process unit (SPU) associated with a logical ring of SPUs. The SPU receives a packet with an address associated with a malicious source, and creates, based on the packet, an entry in a data structure associated with the SPU. The entry includes information associated with the packet. The SPU provides an install message to a next SPU in the logical ring. The install message instructs the next SPU to create the entry in another data structure, and forward the install message to another SPU. The SPU receives the install message from a last SPU, and sets a state of the entry to active in the data structure based on receiving the install message from the last SPU. The SPU performs a particular action on another packet, associated with the malicious source, based on the setting the state of the entry to active.

Abstract: A device may comprise security processing units (SPUs) including a SPU to receive a session request. The SPU may identify global counter information and update counter information. The global counter information may include a global counter identifier and a global counter value. The update counter information may include an update counter identifier and an update counter value. The SPU may identify a global limit associated with the global counter, may determine that the global limit has not been met, and may cause the session to be created. The SPU may create a modified global counter value. The SPU may create a modified update counter value. The SPU may determine that a local update message is required based on the modified update counter value, and may provide the local update message to another SPU. The local update message may include the global counter identifier and the modified global counter value.

Abstract: A method for forming a metal silicide. The method comprises: providing a substrate having a fin, a gate formed on the fin, and spacers formed on opposite sides of the gate; depositing a Ti metal layer; siliconizing the Ti metal layer; and removing unreacted Ti metal layer. As the Ti atoms have relatively stable characteristics, diffusion happens mostly to Si atoms while the Ti atoms rarely diffuse during the thermal annealing. As a result, current leakage can be prevented in a depletion region and thus leakage current of the substrate can be reduced.

Abstract: A MOS transistor with stacked nanowires and a method of manufacturing the same. The transistor may include a stack of cascaded nanowires extending in a first direction on a substrate; a gate stack extending in a second direction across the nanowire stack; source and drain regions disposed on opposite sides of the gate stack in the second direction; and a channel region constituted of the nanowire stack between the source and drain regions. The cascaded nanowires can be formed by repeated operations of etching back, and lateral etching and then filling of grooves, thereby increasing an effective width of the channel, increasing a total area of an effective conductive section, and thus improving a drive current.

Abstract: A device may comprise security processing units (SPUs) including a SPU to receive a session request. The SPU may identify global counter information and update counter information. The global counter information may include a global counter identifier and a global counter value. The update counter information may include an update counter identifier and an update counter value. The SPU may identify a global limit associated with the global counter, may determine that the global limit has not been met, and may cause the session to be created. The SPU may create a modified global counter value. The SPU may create a modified update counter value. The SPU may determine that a local update message is required based on the modified update counter value, and may provide the local update message to another SPU. The local update message may include the global counter identifier and the modified global counter value.

Abstract: Methods of manufacturing stacked nanowires MOS transistors are disclosed. In one aspect, the method includes forming a plurality of fins along a first direction on a substrate. The method also includes forming stack of nanowires constituted of a plurality of nanowires in each of the fins. The method also includes forming a gate stack along a second direction in the stack of nanowires, the gate stack surrounding the stack of nanowires. The method also includes forming source/drain regions at both sides of the gate stack, the nanowires between the respective source/drain regions constituting a channel region. A stack of nanowires may be formed by a plurality of etching back, laterally etching a trench and filling the trench. The laterally etching process includes isotropic dry etching having an internally tangent and lateral etching, and a wet etching which selectively etches along respective crystallographic directions.

Abstract: A semiconductor device includes a fin extending on a substrate along a first direction; a gate extending along a second direction across the fin; and source/drain regions and a gate spacer on the fin at opposite sides of the gate, in which there is a surface layer on the top and/or sidewalls of the fin.

Abstract: A device includes a security process unit (SPU) associated with a logical ring of SPUs. The SPU receives a packet with an address associated with a malicious source, and creates, based on the packet, an entry in a data structure associated with the SPU. The entry includes information associated with the packet. The SPU provides an install message to a next SPU in the logical ring. The install message instructs the next SPU to create the entry in another data structure, and forward the install message to another SPU. The SPU receives the install message from a last SPU, and sets a state of the entry to active in the data structure based on receiving the install message from the last SPU. The SPU performs a particular action on another packet, associated with the malicious source, based on the setting the state of the entry to active.

Abstract: Provided is a method for manufacturing a MOSFET, including: forming a shallow trench isolation (STI) in a semiconductor substrate to define an active region for the MOSFET; performing etching with the STI as a mask, to expose a surface of the semiconductor substrate, and to protrude a portion of the STI with respect to the surface of the semiconductor substrate, resulting in a protruding portion; forming a first spacer on sidewalls of the protruding portion; forming a gate stack on the semiconductor substrate; forming a second spacer surrounding the gate stack; forming openings in the semiconductor substrate with the STI, the gate stack, the first spacer and the second spacer as a mask; epitaxially growing a semiconductor layer with a bottom surface and sidewalls of each of the openings as a growth seed layer; and performing ion implantation into the semiconductor layer to form source and drain regions.

Abstract: A device includes a security process unit (SPU) associated with a logical ring of SPUs. The SPU receives a packet with an address associated with a malicious source, and creates, based on the packet, an entry in a data structure associated with the SPU. The entry includes information associated with the packet. The SPU provides an install message to a next SPU in the logical ring. The install message instructs the next SPU to create the entry in another data structure, and forward the install message to another SPU. The SPU receives the install message from a last SPU, and sets a state of the entry to active in the data structure based on receiving the install message from the last SPU. The SPU performs a particular action on another packet, associated with the malicious source, based on the setting the state of the entry to active.

Abstract: The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located in the fins below the gate stack structures; characterized in that the stress layers have connected parts in the fins and that the channel regions enclose the connected parts.

Abstract: A method for forming a metal silicide. The method comprises: providing a substrate having a fin, a gate formed on the fin, and spacers formed on opposite sides of the gate; depositing a Ti metal layer; siliconizing the Ti metal layer; and removing unreacted Ti metal layer. As the Ti atoms have relatively stable characteristics, diffusion happens mostly to Si atoms while the Ti atoms rarely diffuse during the thermal annealing. As a result, current leakage can be prevented in a depletion region and thus leakage current of the substrate can be reduced.

Abstract: A semiconductor device is provided that has a plurality of Fin structures extending on a substrate along a first direction; a gate stack structure extending on the substrate along a second direction and across the plurality of Fin structures, wherein the gate stack structure comprises a gate conductive layer and a gate insulating layer, and the gate conductive layer is formed by a doped poly-semiconductor; trench regions in the plurality of Fin structures and beneath the gate stack structure; and source/drain regions on the plurality of Fin structures and at both sides of the gate stack structure along the first direction. A method of manufacturing a semiconductor device is also provided.

Abstract: A MOS transistor with stacked nanowires and a method of manufacturing the same. The transistor may include a stack of cascaded nanowires extending in a first direction on a substrate; a gate stack extending in a second direction across the nanowire stack; source and drain regions disposed on opposite sides of the gate stack in the second direction; and a channel region constituted of the nanowire stack between the source and drain regions. he cascaded nanowires can be formed by repeated operations of etching back, and lateral etching and then filling of grooves, thereby increasing an effective width of the channel, increasing a total area of an effective conductive section, and thus improving a drive current.

Abstract: An apparatus and a method for epitaxially growing sources and drains of a FinFET device. The apparatus comprises: a primary chamber; a wafer-loading chamber; a transfer chamber provided with a mechanical manipulator for transferring the wafer; an etching chamber for removing a natural oxide layer on the surface of the wafer and provided with a graphite base for positioning the wafer; at least one epitaxial reaction chamber; a gas distribution device for supplying respective gases to the primary chamber, the wafer loading chamber, the transfer chamber, the etching chamber and the epitaxial reaction chamber; and a vacuum device. The wafer loading, transfer, etching, and epitaxial reaction chambers are all positioned within the primary chamber. The apparatus integrates the etching chamber and epitaxial reaction chamber to remove the natural oxide layer on the surface of the wafer in a condition of isolating water and oxygen before the epitaxial reaction has occurred.

Abstract: A FinFET device and a method for manufacturing the same. The FinFET device includes a plurality of fins each extending in a first direction on a substrate; a plurality of gate stacks each being disposed astride the plurality of fins and extending in a second direction; a plurality of source/drain region pairs, respective source/drain regions of each source/drain region pair being disposed on opposite sides of the each gate stack in the second direction; and a plurality of channel regions each comprising a portion of a corresponding fin between the respective source/drain regions of a corresponding source/drain pair, wherein the each fin comprises a plurality of protruding cells on opposite side surfaces in the second direction.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming, on a substrate, a plurality of fins extending along a first direction; forming, on the fins, a dummy gate stack extending along a second direction; forming a gate spacer on opposite sides of the dummy gate stack in the first direction; epitaxially growing raised source/drain regions on the top of the fins on opposite sides of the gate spacer in the first direction; performing lightly-doping ion implantation through the raised source/drain regions with the gate spacer as a mask, to form source/drain extension regions in the fins on opposite sides of the gate spacer in the first direction; removing the dummy gate stack to form a gate trench; and forming a gate stack in the gate trench.

Abstract: A method for manufacturing a dual metal CMOS device comprising: forming a first type metal work function modulation layer in the first gate trench and the second gate trench; forming a second type work function metal diffusion source layer in the first gate trench and the second gate trench; forming a heat isolation layer that shields the region of the first type device; and thermally annealing the regions where the first type device and the second type device are located.

Abstract: An CMOS device comprises a plurality of NMOS transistors and a plurality of PMOS transistors, each of which comprises a gate stack constituted of a gate insulating layer and a gate metal layer on a substrate, a source/drain region in the substrate on both sides of the gate stack and a channel region below the gate stack, wherein the gate metal layer of each NMOS transistor comprising a first barrier layer, an NMOS work function adjusting layer, a second barrier layer, and a filling layer, and wherein the gate metal layer of each PMOS transistor comprising a first barrier layer, a PMOS work function adjusting layer, an NMOS work function adjusting layer, a second barrier layer, and a filling layer, and wherein the first barrier layer in the gate metal layer of the NMOS transistor and the first barrier layer in the gate metal layer of the PMOS transistor contain a doping ion to finely adjust the work function.