Abstract: A DC-DC converter circuit with selectable working modes is disclosed. Compared with the traditional chip that works in one mode, the DC-DC converter with selectable working modes adds only a mode selection circuit, so that the chip can work in voltage control mode or current control mode. On the one hand, the applications of the chip are more extensive, and on the other hand, when the applications are different, the cost of developing a DC-DC converter with selectable working mode is greatly reduced compared with the traditional DC-DC converter.

Abstract: A voltage-to-time converter (VTC) for a time-domain analog-to-digital converter is disclosed, which provides a time-domain analog-to-digital converter (T-ADC) with low power consumption and high precision. By combining the advantages of current-starving technology, current mirror technology, and body biasing technology, compared with the traditional structure, the VTC and T-ADC achieve excellent performance, such as low power consumption, high linearity, wide input dynamic range, and strong anti-interference to PVT variations. Compared with the traditional voltage-to-time converter, the disclosed voltage-to-time converter has a wider input dynamic range and higher linearity. The input voltage is connected to transistors in the circuit as a body bias, resulting in a very small body current, and no apparent increase in power consumption. The design of a low-power voltage-to-time converter is realized.

Abstract: A method of arranging a capacitor array of a successive approximation register analog-to-digital converter in a successive approximation process, the method including: splitting a binary capacitor array into unit capacitors, then sorting, grouping, and rotating the original binary capacitive array involved in successive approximation conversion.

Abstract: A method of arranging a capacitor array of a successive approximation register analog-to-digital converter in a successive approximation process, the method including: splitting a binary capacitor array into unit capacitors, then sorting, grouping, and rotating the original binary capacitive array involved in successive approximation conversion.