METHOD OF ARRANGING CAPACITOR ARRAY OF SUCCESSIVE APPROXIMATION REGISTER ANALOGTODIGITAL CONVERTER
A method of arranging a capacitor array of a successive approximation register analogtodigital converter in a successive approximation process, the method including: splitting a binary capacitor array into unit capacitors, then sorting, grouping, and rotating the original binary capacitive array involved in successive approximation conversion.
Pursuant to 35 U.S.C.§ 119 and the Paris Convention Treaty, this application claims foreign priority to Chinese Patent Application No. 201711039954.3 filed Oct. 31, 2017, the contents of which and any intervening amendments thereto are incorporated herein by reference. Inquiries from the public to applicants or assignees concerning this document or the related applications should be directed to: Matthias Scholl P. C., Attn.: Dr. Matthias Scholl Esq., 245 First Street, 18th Floor, and Cambridge, Mass. 02142.
BACKGROUND OF THE INVENTION Field of the InventionThis disclosure relates to a successive approximation register analogtodigital converters (SAR ADC), and more particularly to a method of arranging a capacitor array of a successive approximation register analogtodigital converter in a successive approximation process.
Description of the Related ArtSmart sensors are devices that contain integrated transducers, signal conditioning modules, and processing modules. Smart sensors are applied in such fields as precision instruments, medical instruments, communication, radar, aerospace, electronic countermeasures, security screening systems, fault detection, and earthquake detection. In recent years, with the rapid development of smart sensors, research on embedded modules such as sensors, amplifiers, and analogtodigital converters (ADCs) for smart sensors has drawn much attention.
The architectures of mainstream NyquistRate ADCs include Flash ADC, successive approximation register (SAR) ADC, pipeline ADC, and SigmaDelta ADC. Spuriousfree dynamic range (SFDR), signaltonoise and distortion ratio (SNDR), and signaltonoise ratio (SNR) are dynamic parameters that evaluate the linearity of the ADC. Higher dynamic parameters mean higher linearity.
Flash ADC can only be used for low resolution and high sampling rate application. Pipeline and SigmaDelta ADCs are not appropriate for low power consumption design as they require using opamps. SAR ADC uses a binary algorithm to convert the input analog signal into the output digital signal. As shown in
The highresolution SAR ADC mainly adopts a combined capacitorresistor network, as shown in
As shown in
In view of the abovedescribed problems, it is an objective of the invention to a method of arranging a capacitor array of a successive approximation register analogtodigital converter that can reduce unnecessary losses such as design complexity, chip area, power consumption, and speed of a SAR ADC. Another objective of the invention is to reduce the capacitor mismatch of a SAR ADC without using additional capacitors.
To achieve the above objective, according to one aspect of the invention, there is provided a method of arranging a capacitor array of a successive approximation register analogtodigital converter in a successive approximation process, the method comprising:

 Step 1: separating a 6bit binary capacitive DAC of 64 unit capacitors (64C) into 64 independent capacitors;
 Step 2: sorting the 64 independent capacitors from highest to lowest by capacitance, then using 64 digital codes from C1 to C64 to numbering the 64 independent capacitors sorted from highest to lowest by capacitance, and then recording the 64 digital codes and corresponding capacitance values of the 64 independent capacitors in a register;
 Step 3: dividing the 64 independent capacitors into four groups as follows:
 Group 1 comprising C1, C64, C3, C62, C5, C60, C7, C58, C9, C56, C11, C54, C13, C52, C15, and C50;
 Group 2 comprising C17, C48, C19, C46, C21, C44, C23, C42, C25, C40, C27, C38, C29, C36, C31, and C34;
 Group 3 comprising C32, C33, C30, C35, C28, C37, C26, C39, C24, C41, C22, C43, C20, C45, C18, and C47; and
 Group 4 comprising C16, C49, C14, C51, C12, C53, C10, C55, C8, C57, C6, C59, C4, C61, C2, and C63; and
 Step 4: in a successive approximation conversion process, selecting two groups to constitute a largest capacitor 32C, select one group from the remaining two groups to constitute a second largest capacitor 16C, selecting first 8 capacitors in the last group to constitute a capacitor 8C, selecting the next 9th12th capacitors in the last group to constitute a capacitor 4C, selecting the 13th and 14th capacitors in the last group to constitute a capacitor 2C, and selecting the last two capacitors to constitute two capacitors C and C, respectively.
In a class of this embodiment, step 4 is carried out as follows:

 in a first successive approximation conversion process, Group 1 and Group 2 are selected to constitute the largest capacitor 32C, Group 3 is selected to constitute the second largest capacitor 16C, Group 4 is selected to constitute capacitors 8C, 4C, 2C, C, and C;
 in a second successive approximation conversion process, Group 4 and Group 1 are selected to replace the largest capacitor 32C, Group 2 is selected to replace the second largest capacitor 16C, Group 3 is selected to replace capacitors 8C, 4C, 2C, C, and C;
 in a third successive approximation conversion process, Group 3 and Group 4 are selected to replace the largest capacitor 32C, Group 1 is selected to replace the second largest capacitor 16C, Group 2 is selected to replace capacitors 8C, 4C, 2C, C, and C;
 in a fourth successive approximation conversion process, Group 2 and Group 3 are selected to replace the largest capacitor 32C, Group 4 is selected to replace the second largest capacitor 16C, Group 1 is selected to replace capacitors 8C, 4C, 2C, C, and C;
 in a fifth successive approximation conversion process, Group 3 and Group 4 are selected to replace the largest capacitor 32C, Group 1 is selected to replace the second largest capacitor 16C, Group 2 is selected to replace capacitors 8C, 4C, 2C, C, and C; and
in a sixth successive approximation conversion process, Group 4 and Group 1 are selected to replace the largest capacitor 32C, Group 2 is selected to replace the second largest capacitor 16C, Group 3 is selected to replace capacitors 8C, 4C, 2C, C, and C.
In a class of this embodiment, the abovementioned six successive approximation conversion processes are repeated in loops.
Advantages of the method according to embodiments of the disclosure are summarized as follows: by sorting, combining, and adjusting the capacitive array, the capacitor mismatch can be reduced. Compared with the conventional methods, the ADC mismatch error is reduced and the accuracy is improved. Compared with the conventional technology, this invention does not require additional capacitors.
The capacitor optimization method of the invention is for enhancing the linearity of capacitorresistor combined SAR ADC for smart sensor applications. The capacitor optimization method of the invention includes splitting a binary capacitor array into unit capacitors and then sorting and grouping, and finally, according to certain rule, rotating the original binary capacitive array involved in successive approximation conversion. The method of the invention applied to a traditional 14bit resistorcapacitor successive approximation ADC as shown in
The optimization method proposed in this invention is shown in
The reason why the linearity can be improved by this invention lies in the following two aspects.
Firstly, according to statistical principles, the standard deviation of the distribution function after sorting is reduced so that the equivalent capacitor mismatch error is reduced, according to the distribution function shown in
Secondly, the capacitor mismatch error accumulates continuously in a traditional SAR ADC. In order to eliminate the accumulation, the capacitive array optimization technique proposed in this invention sorts the unit capacitors firstly, then divides the unit capacitors into 4 groups, alternates the 4 groups of capacitors in sequence according to six different arrangements. This invention does not need to introduce an extra operational amplifier to conduct noise shaping, does not require any calibration algorithms, and does not require extra capacitors. The accumulated mismatch error is quantified by the variance σ_{INL}^{2 }of INL:
in which N_{T }is the total number of capacitors; for Nbit SAR ADC, N_{T}=2^{N}, n is the number of used components; for the traditional capacitive array, when n is equal to N_{T}/2, there is the formula as follows:
which demonstrates that the maximum error of the traditional SAR ADC occurs at the midpoint, and the maximum integral nonlinearity error is
According to this invention, four groups of capacitors rotates in turn, it is assumed that the digital code n_{1}, n_{2}, n_{3 }, and n_{4 }represent conversion results for the first, the second, the third, and the fourth conversion, respectively, and the variance for the four times of conversion is: σ_{n1234}^{2}=(n_{1}+n_{2}n_{3}+n_{4})σ_{u}^{2}.
When n_{1234}=n_{1}+n_{2}+n_{3}+n_{4}, the INL variance is calculated as follows:
in which N_{T }is the total number of capacitors, σ_{u }is the mismatch error of unit capacitor. When n_{1234}=N_{T}/2, σ_{INL}_{groud}_{,max }is calculated as follows:
Comparing (2) and (4), it demonstrates that the rotation of the four groups of capacitors reduces the integrated nonlinear error to one quarter of that of the traditional SAR ADC, and as well known, the reduction of integrated nonlinear error corresponds to increase of SFDR.
In conclusion, grouping and sorting results in a reduction of the capacitor equivalent mismatch error. The capacitor replacement rule avoids the error accumulation, thus improving the linearity. Therefore, this invention combines the advantages of two methods to achieve a substantial increase in linearity.
Table 1 summarizes the performance comparison among the traditional method, the capacitor reconfiguring method proposed in Fan, and the capacitive array optimization technique of this invention. For capacitor reconfiguring technique, extra 64 capacitors were added to the capacitive array, and the difference between the maximum value and minimum value of SFDR in the set of values obtained by the Monte Carlo simulation reaches 26.6 dB with σ_{u}=0.2%, the capacitive array optimization technique of this invention makes the SFDR more concentrated in the center, and reduces the difference between maximum value and minimum value of SFDR to only 6 dB with σ_{u}=0.2%, which means more stable performance enhancement. It is worth to mention that the concentration becomes more obvious for the SNDR and SNR results. In a word, the capacitive array optimization technique of this invention achieves excellent performance enhancement without extra capacitors and without sacrificing the sampling rate of conventional SAR ADC.
Compared with the conventional resistorcapacitor SAR ADC, this invention improves the average SFDR by about 17.2 dB and the average SNDR by about 8.6 dB with σ_{u}=0.2%. Although the capacitor reconfiguring proposed in Fan can also improve SFDR, but an additional 64 extra capacitors are needed. This invention avoids the addition of 64 extra unit capacitors, further reduces the power consumption and silicon area.
In this invention, a novel capacitor array optimization scheme is proposed based on conventional capacitorresistor SAR ADC. By sorting, grouping, and rotating the capacitive array, the mismatch errors of the ADC can be counteracted. Compared with the traditional noise shaping technology or the LeastMeanSquare (LMS) calibration algorithm, the control logic of this invention is much easier, and the hardware cost is much smaller, reducing the power consumption and the area at the same time. Compared with the capacitor reconfiguring method of Fan, this invention avoids the introduction of additional capacitors but achieves the dynamic parameters nearly similar to the capacitor reconfiguring method.
Unless otherwise indicated, the numerical ranges involved in the invention include the end values. While particular embodiments of the invention have been shown and described, it will be obvious to those skilled in the art that changes and modifications may be made without departing from the invention in its broader aspects, and therefore, the aim in the appended claims is to cover all such changes and modifications as fall within the true spirit and scope of the invention.
Claims
1. (canceled)
2. A method of arranging a capacitor array of a successive approximation register analogtodigital converter, the method comprising: wherein 4) comprises six successive approximation conversion processes as follows:
 1) separating a 6bit binary capacitive digitaltoanalog converter (DAC) of 64 unit capacitors into 64 independent capacitors;
 2) sorting the 64 independent capacitors from highest to lowest by capacitance, then using 64 digital codes from C1 to C64 to number the 64 independent capacitors sorted from highest to lowest by capacitance, and then recording the 64 digital codes and corresponding capacitance values of the 64 independent capacitors in a register;
 3) dividing the 64 independent capacitors into four groups as follows: i) Group 1 comprising C1, C64, C3, C62, C5, C60, C7, C58, C9, C56, C11, C54, C13, C52, C15, and C50; ii) Group 2 comprising C17, C48, C19, C46, C21, C44, C23, C42, C25, C40, C27, C38, C29, C36, C31, and C34; iii) Group 3 comprising C32, C33, C30, C35, C28, C37, C26, C39, C24, C41, C22, C43, C20, C45, C18, and C47; and iv) Group 4 comprising C16, C49, C14, C51, C12, C53, C10, C55, C8, C57, C6, C59, C4, C61, C2, and C63; and
 4) in a successive approximation conversion process, selecting two of the four groups to constitute a largest capacitor 32C, selecting a first of the remaining two of the four groups to constitute a second largest capacitor 16C, selecting 1th8th capacitors in a second of the remaining two of the four groups to constitute a capacitor 8C, selecting 9th12th capacitors in the second of the remaining two of the four groups to constitute a capacitor 4C, selecting 13th and 14th capacitors in the second of the remaining two of the four groups to constitute a capacitor 2C, and selecting 15th and 16th capacitors in the second of the remaining two of the four groups to constitute two capacitors C and C, respectively;
 in a first successive approximation conversion process, Group 1 and Group 2 are selected to constitute the largest capacitor 32C, Group 3 is selected to constitute the second largest capacitor 16C, Group 4 is selected to constitute the capacitors 8C, 4C, 2C, C, and C;
 in a second successive approximation conversion process, Group 4 and Group 1 are selected to replace the largest capacitor 32C, Group 2 is selected to replace the second largest capacitor 16C, Group 3 is selected to replace the capacitors 8C, 4C, 2C, C, and C;
 in a third successive approximation conversion process, Group 3 and Group 4 are selected to replace the largest capacitor 32C, Group 1 is selected to replace the second largest capacitor 16C, Group 2 is selected to replace the capacitors 8C, 4C, 2C, C, and C;
 in a fourth successive approximation conversion process, Group 2 and Group 3 are selected to replace the largest capacitor 32C, Group 4 is selected to replace the second largest capacitor 16C, Group 1 is selected to replace the capacitors 8C, 4C, 2C, C, and C;
 in a fifth successive approximation conversion process, Group 3 and Group 4 are selected to replace the largest capacitor 32C, Group 1 is selected to replace the second largest capacitor 16C, Group 2 is selected to replace the capacitors 8C, 4C, 2C, C, and C; and
 in a sixth successive approximation conversion process, Group 4 and Group 1 are selected to replace the largest capacitor 32C, Group 2 is selected to replace the second largest capacitor 16C, Group 3 is selected to replace the capacitors 8C, 4C, 2C, C, and C; and
 the six successive approximation conversion processes are repeated in loops.
Type: Application
Filed: Aug 28, 2018
Publication Date: May 2, 2019
Inventors: Hua FAN (Chengdu), Jingxuan YANG (Chengdu), Quanyuan FENG (Chengdu), Dagang LI (Chengdu), Daqian HU (Chengdu), Yuanjun CEN (Chengdu), Hadi HEIDARI (Chengdu), Franco MALOBERTI (Chengdu), Jingtao LI (Chengdu), Huaying SU (Chengdu)
Application Number: 16/114,300